Results 21 to 30 of about 106,345 (262)
DReAM: Per-task DRAM energy metering in multicore systems [PDF]
, 2014 Interaction across applications in DRAM memory impacts its energy consumption. This paper makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations, such as per-task energy-aware ...
Abella Ferrer, Jaume +4 more
core +1 more source
Emulating and evaluating hybrid memory for managed languages on NUMA hardware [PDF]
, 2019 Non-volatile memory (NVM) has the potential to become a mainstream memory technology and challenge DRAM. Researchers evaluating the speed, endurance, and abstractions of hybrid memories with DRAM and NVM typically use simulation, making it easy to ...
Akram, Shoaib +3 more
core +1 more source
PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM [PDF]
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2021 Deep Neural Networks (DNNs) have transformed the field of machine learning and are widely deployed in many applications involving image, video, speech and natural language processing. The increasing compute demands of DNNs have been widely addressed through Graphics Processing Units (GPUs) and specialized accelerators.
Sourjya Roy +2 more
openaire +2 more sources
A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors
Micromachines, 2019 A full three-dimensional technology-computer-aided-design-based reliability prediction model was proposed for dynamic random-access memory (DRAM) storage capacitors.
Woo Young Choi +5 more
doaj +1 more source
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation [PDF]
, 2016 Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, which fails to hold below 0 ...
Amat Bertran, Esteve +3 more
core +3 more sources
, 2016 This is a summary of the original paper, entitled "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture" which appears in HPCA ...
Lee, Donghyuk +5 more
openaire +2 more sources
Nanomaterials, 2022 In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using ...
Hee Dae An +11 more
doaj +1 more source
Implementation and Optimization of Apache Spark Cache System Based on Mixed Memory [PDF]
Jisuanji kexue, 2023 With increasing data scale in the “big data era”,in-memory computing frameworks have grown significantly.The mainstream in-memory computing framework Apache Spark uses memory to cache intermediate results,which greatly improves data processing ...
WEI Sen, ZHOU Haoran, HU Chuang, CHENG Dazhao
doaj +1 more source
Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories
, 2020 Modern computing systems are embracing hybrid memory comprising of DRAM and non-volatile memory (NVM) to combine the best properties of both memory technologies, achieving low latency, high reliability, and high density.
Antognetti P. +32 more
core +1 more source
Energy-Efficient Streaming Using Non-volatile Memory [PDF]
, 2008 The disk and the DRAM in a typical mobile system consume a significant fraction (up to 30%) of the total system energy. To save on storage energy, the DRAM should be small and the disk should be spun down for long periods of time.
Dijk, Hylke W. van +2 more
core +2 more sources