Results 191 to 200 of about 1,280 (239)
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Efficient FeFET Crossbar Accelerator for Binary Neural Networks
2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2020This paper presents a novel ferroelectric field-effect transistor (FeFET) in-memory computing architecture dedicated to accelerate Binary Neural Networks (BNNs). We present in-memory convolution, batch normalization and dense layer processing through a grid of small crossbars with reduced unit size, which enables multiple bit operation and value ...
Taha Soliman +7 more
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Novel Ferroelectric Gate Field-Effect Transistors (FeFETs); Controlled Polarization-Type FeFETs
2020Controlled-polarization-type ferroelectric-gate thin film transistors (FeTFTs), which utilize the interaction between the polarizations of a polar semiconductor and a ferroelectric layer, have been proposed. When the polarizations align head-to-head, electrons that correspond to the sum of the polarizations are induced at the interface between the ...
Norifumi Fujimura, Takeshi Yoshimura
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Retention and Endurance of FeFET Memory Cells
2019 IEEE 11th International Memory Workshop (IMW), 2019Despite decades of R&D, the single-transistor (1-T) memory cell based on ferroelectric-gated Field-Effect-Transistor (FeFET) has failed to commercialize as of this writing, largely due to the inadequate retention time. The recent advent of the HfO 2 -based ferroelectrics, however, promises to change that.
T.P. Ma, Nanbo Gong
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Reconfiguring the Mux-Based Arbiter PUF using FeFETs
2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021Physical Unclonable Functions (PUFs) are lightweight security primitives that exploit complex manufacturing variations in integrated circuits to extract secret keys. It is well-established that the unique keys generated by the mux-based arbiter PUF can be predicted accurately using logistic regression (LR), provided a set of challenge-response pairs ...
Srinivasa Ramanujam, Wayne P. Burleson
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FeMPIM: A FeFET-Based Multifunctional Processing-in-Memory Cell
IEEE Transactions on Circuits and Systems II: Express BriefsInternational audienceThe Von-Neumann memory wall bottleneck that keeps expanding is mainly caused by the frequent data transfer between the main memory and the processor.
Aibin Yan +7 more
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Analysis and Characterization of Defects in FeFETs
2023 IEEE International Test Conference (ITC), 2023Dhruv Thapar +4 more
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Hardware Emulation of FeFET On FPGA
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022Paul-Antoine, Matrangolo +3 more
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2015 IEEE International Electron Devices Meeting (IEDM), 2015
Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film.
H. Mulaosmanovic +18 more
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Recent discovery of ferroelectricity in HfO2 thin films paved the way for demonstration of ultra-scaled 28 nm Ferroelectric FETs (FeFET) as non-volatile memory (NVM) cells [1]. However, such small devices are inevitably sensible to the granularity of the polycrystalline gate oxide film.
H. Mulaosmanovic +18 more
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2019 Symposium on VLSI Technology, 2019
In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(\text{A}_{\text{FE}}/\text{A}_{\text{IL}})$ of ferroelectric layer to ...
Vita Pi-Ho Hu +8 more
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In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(\text{A}_{\text{FE}}/\text{A}_{\text{IL}})$ of ferroelectric layer to ...
Vita Pi-Ho Hu +8 more
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FeFET-Based In-Memory Hyperdimensional Encoding Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023Qingrong Huang +5 more
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