Results 171 to 180 of about 723 (223)

Hafnium-Based Ferroelectric Diodes for Logic-in-Memory Application. [PDF]

open access: yesMicromachines (Basel)
Han S   +10 more
europepmc   +1 more source

On the Reliability of FeFET On-Chip Memory

IEEE Transactions on Computers, 2022
FeFET is a promising technology for non-volatile on-chip memories. It is rapidly attracting an ever-increasing attention from industry. The advantage of FeFETs is full compatibility with the existing CMOS process beside their low power consumption. To enable ultra-dense memories, 1-FeFET AND arrays were proposed in which a memory cell is formed from a ...
Paul R. Genssler   +3 more
openaire   +2 more sources

Variability sources and reliability of 3D — FeFETs

2021 IEEE International Reliability Physics Symposium (IRPS), 2021
Discovery of ferroelectricity (FE) in binary oxides enables the advent of FE memories and a plethora of novel CMOS compatible building blocks spanning from the logic domain to high-density storage and neuromorphic computing. In this paper we develop the first comprehensive model of vertical Ferroelectric Field Effect Transistor, V-FeFET, to identify ...
Pesic M.   +12 more
openaire   +1 more source

Computing in memory with FeFETs

Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Data transfer between a processor and memory frequently represents a bottleneck with respect to improving application-level performance. Computing in memory (CiM), where logic and arithmetic operations are performed in memory, could significantly reduce both energy consumption and computational overheads associated with data transfer.
Dayane Alfenas Reis   +2 more
openaire   +1 more source

FeFET and NCFET for Future Neural Networks: Visions and Opportunities

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021
The goal of this special session paper is to introduce and discuss different emerging technologies for logic circuitry and memory as well as new lightweight architectures for neural networks. We demonstrate how the ever-increasing complexity in Artificial Intelligent (AI) applications, resulting in an immense increase in the computational power ...
Mikail Yayla   +5 more
openaire   +1 more source

Efficient FeFET Crossbar Accelerator for Binary Neural Networks

2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2020
This paper presents a novel ferroelectric field-effect transistor (FeFET) in-memory computing architecture dedicated to accelerate Binary Neural Networks (BNNs). We present in-memory convolution, batch normalization and dense layer processing through a grid of small crossbars with reduced unit size, which enables multiple bit operation and value ...
Taha Soliman   +7 more
openaire   +1 more source

FeFETs for Neuromorphic Systems

2020
Neuromorphic engineering represents one of the most promising computing paradigms for overcoming the limitations of the present-day computers in terms of energy efficiency and processing speed. While traditional neuromorphic circuits are based on complementary metal oxide semiconductor (CMOS) transistors and large capacitors, the recently emerging ...
Halid Mulaosmanovic   +2 more
openaire   +1 more source

Novel Ferroelectric Gate Field-Effect Transistors (FeFETs); Controlled Polarization-Type FeFETs

2020
Controlled-polarization-type ferroelectric-gate thin film transistors (FeTFTs), which utilize the interaction between the polarizations of a polar semiconductor and a ferroelectric layer, have been proposed. When the polarizations align head-to-head, electrons that correspond to the sum of the polarizations are induced at the interface between the ...
Norifumi Fujimura, Takeshi Yoshimura
openaire   +1 more source

PZT Based MFS Structure for FeFET

Integrated Ferroelectrics, 2003
Fabrication and properties of lead zirconate titanate (PZT) thin films have been studied for Metal-Ferroelectric-Semiconductor FET (MFSFET) devices. PZT based MFS capacitors using lead titanate (PT) as seeding layers have been respectively prepared on p-type ⟨111⟩ and n-type ⟨100⟩ silicon wafers directly by a sol-gel method.
Tian-Qi Shao   +8 more
openaire   +1 more source

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