Results 181 to 190 of about 723 (223)
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Retention and Endurance of FeFET Memory Cells
2019 IEEE 11th International Memory Workshop (IMW), 2019Despite decades of R&D, the single-transistor (1-T) memory cell based on ferroelectric-gated Field-Effect-Transistor (FeFET) has failed to commercialize as of this writing, largely due to the inadequate retention time. The recent advent of the HfO 2 -based ferroelectrics, however, promises to change that.
T.P. Ma, Nanbo Gong
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Reconfiguring the Mux-Based Arbiter PUF using FeFETs
2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021Physical Unclonable Functions (PUFs) are lightweight security primitives that exploit complex manufacturing variations in integrated circuits to extract secret keys. It is well-established that the unique keys generated by the mux-based arbiter PUF can be predicted accurately using logistic regression (LR), provided a set of challenge-response pairs ...
Srinivasa Ramanujam, Wayne P. Burleson
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Understanding the memory window in 1T-FeFET memories: a depolarization field perspective
2021 IEEE International Memory Workshop (IMW), 2021We present a physics-based prediction of the progressive V TH shift on fabricated Si:HfO 2 -FeFETs during Incremental Step Pulse Programming, with the help of our in-house, hardware-validated FeFET compact model. Our study confirms that the depolarization field across the FE layer strongly constrains the retained polarization in the gate stack after ...
K. Kaczmarek +7 more
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2019 Symposium on VLSI Technology, 2019
In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(\text{A}_{\text{FE}}/\text{A}_{\text{IL}})$ of ferroelectric layer to ...
Vita Pi-Ho Hu +8 more
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In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio $(\text{A}_{\text{FE}}/\text{A}_{\text{IL}})$ of ferroelectric layer to ...
Vita Pi-Ho Hu +8 more
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Hardware Emulation of FeFET On FPGA
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022Paul-Antoine, Matrangolo +3 more
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Analysis and Characterization of Defects in FeFETs
2023 IEEE International Test Conference (ITC), 2023Dhruv Thapar +4 more
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Scalable Complementary FeFET CAM Design
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023Omar Bekdache +5 more
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Influence of gate-source/drain overlap on FeFETs
Solid-State Electronics, 2023CHANGHA KIM, Dong-Oh Kim, Woo Young Choi
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FeFET-Based In-Memory Hyperdimensional Encoding Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023Qingrong Huang +5 more
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FeFETs for Near-Memory and In-Memory Compute
2021 IEEE International Electron Devices Meeting (IEDM), 2021Saveef Salahuddin +5 more
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