Results 131 to 140 of about 1,221 (182)

Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold

Microelectronic Engineering, 1992
Simulations of, drain Current and intrinsic gate capacitances of nMOS/GAA transistors are presented and compared with experimental results. On the basis of the insight they give into the unique behaviour of these devices, new hypotheses have emerged and yielded an analytical model valid around the threshold voltage.
P. Francis, A. Terao, D. Flandre, F. Van de Wiele   +3 more
openaire   +1 more source

ESD characterization of gate-all-around (GAA) Si nanowire devices

2015 IEEE International Electron Devices Meeting (IEDM), 2015
In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring ...
S.-H. Chen, D. Linten, G. Hellings, A. Veloso, M. Scholz, R. Boschke, G. Groeseneken, N. Collaert, A. Thean   +8 more
openaire   +1 more source

Scatterometry for gate all around (GAA) technology enablement (Conference Presentation)

Metrology, Inspection, and Process Control for Microlithography XXXII, 2018
Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration ...
Anne-Laure Charley, Hans Mertens, Naoto Horiguchi, Philippe Leray, Nivea Figueiró, Matthew Sendelbach, Roy Koret, Avron Ger, Shay Wolfling   +8 more
openaire   +1 more source

Effects of total-dose irradiation on gate-all-around (GAA) devices

IEEE Transactions on Nuclear Science, 1993
The response of gate-all-around (GAA) MOS transistors to dose irradiation is quite different from that observed on other types of silicon-on-insulator (SOI) MOSFETs. In regular SOI MOSFETs, edge leakage increases substantially faster than the main transistor leakage upon creation of oxide charges due to the irradiation.
J.-P. Colinge, A. Terao
openaire   +1 more source

Dual Gate Junctionless Gate-All-Around (JL-GAA) FETs using Hybrid Structured Channels

2020 International Conference for Emerging Technology (INCET), 2020
In this work, the concept of hybrid structured channel is proposed to reduce the short channel effect (SCE), while still permitting high current through the channel. 5nm Dual gate junctionless gate-all-around (JL-GAA) FET using two different hybrid structured channels (i.e. concentric cylindrical and zigzag structures) were compared.
Caleb Meriga, Ravi Teja Ponnuri, B. Vamsi Krishna, Shaik Ahmad Saidulu, M. Durga Prakesh   +4 more
openaire   +1 more source

Investigation on cylindrical gate-all-around (GAA) tunnel FETS scaling

2017 IEEE 30th International Conference on Microelectronics (MIEL), 2017
The present work deals with the study and investigation on the GAA Tunnel FET electrical parameters under varying physical conditions, especially, channel thickness t si and length, as well as oxide thickness t ox . Moreover, the effect of the channel doping concentration and the gate work function Φ m .
M. Kessi, A. Benfdila, A. Lakhlef
openaire   +1 more source

Modelling and simulation of Si and InAs gate all around (GAA) nanowire transistors

2015 Annual IEEE India Conference (INDICON), 2015
Owing to the large increase number of transistors in the CMOS logic due to the unending demand for increase in speed of electronic devices and also low power consumptions, it is becoming difficult to incorporate all the small scaled transistors onto one single plane.
Neel Chatterjee, Sujata Pandey
openaire   +1 more source

vfTLP characteristics of ESD devices in Si gate-all-around (GAA) nanowires

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2016
Beyond 7nm nodes, gate-all-around (GAA) nanowire (NW) is a promising device architecture. However, new architecture can result in intrinsic ESD performance degradation. In this work, we study vfTLP characteristics of GAA ESD devices. Transient analysis bring an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.
Shih-Hung Chen, Dimitri Linten, Geert Hellings, Anabela Veloso, Mirko Scholz, Roman Boschke, Guido Groeseneken, Nadine Collaert, Naoto Horiguchi, Aaron Thean   +9 more
openaire   +1 more source

Novel Architecture in Gate-All-Around (GAA) MOSFET with High-k Dielectric for Biomolecule Detection

2021
In this chapter, an investigative unique structure of reconfigurable nanowire-based GAA-MOSFET has been developed, which works as biosensor to notice biomolecules such as DNA, protein, cell, enzyme, etc. It performs as both n-type and p-type depending on the polarization of the applied biasing because of its reconfigurable behavior.
Bhol, Krutideepa, Jena, Biswajit, Nanda, Umakanta, Tayal, Shubham, Jain, Amit Kumar   +4 more
openaire   +1 more source

Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET

Journal of Nano Research, 2019
The paper proposes analytical model for Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA-MOSFET) for germanium channel including quantum mechanical effects. It is achieved by solving coupled Schrodinger-Poisson’s equation using variational approach. The proposed model takes quantum confinement effects to obtain charge centroid and
P. Vimala, N.R. Nithin Kumar
openaire   +1 more source