Results 121 to 130 of about 1,221 (182)

The Planar Core-Shell Junctionless MOSFET. [PDF]

open access: yesMicromachines (Basel)
Dou C   +14 more
europepmc   +1 more source

Integration and electrical evaluation of WS<sub>2</sub> and MoS<sub>2</sub> fets in a 300 mm pilot line. [PDF]

open access: yesDiscov Electron
Schram T   +15 more
europepmc   +1 more source

Design optimization of gate-all-around (GAA) MOSFETs

IEEE Nanotechnology Magazine, 2006
The design of gate-all-around (GAA) MOSFETs was optimized and compared with that of double-gate MOSFETs. We discussed the optimal ratio of the fin width to the gate length and investigated short-channel effects of GAA MOSFETs. Using three-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width ...
Byung Park, Woo Young Choi, Ju Hee Park
exaly   +2 more sources

Realization of Gate-All-Around (GAA) SOI MOSFET Using Replacement Gate Mask

2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007
This paper describes a novel fabrication process of achieving the gate-all-around (GAA) MOSFET device using the replacement gate mask method. In this process, the masking step for the isotropic etch of the bottom gate was replaced by a replacement gate masking step together with a series of processes.
C M Ng
exaly   +2 more sources

Drain current model for a gate all around (GAA) p–n–p–n tunnel FET

Microelectronics Journal, 2013
Abstract A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths.
Rakhi Narang   +2 more
exaly   +2 more sources

AFM characterization for Gate-All-Around (GAA) devices

Metrology, Inspection, and Process Control for Microlithography XXXIV, 2020
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the ...
Mary A. Breton   +8 more
openaire   +1 more source

Characteristics of GaN-Based Nanowire Gate-All-Around (GAA) Transistors

Journal of Nanoscience and Nanotechnology, 2020
We investigate the DC, C–V, and pulse performances in GaN-based nanowire gate-all-around (GAA) transistors with two kinds of geometry: one is AlGaN/GaN heterostructure with two dimensional electron gas (2DEG) channel and the other is only GaN layer without 2DEG channel.
Ki-Sik, Im   +6 more
openaire   +2 more sources

Lateral gate-all-around (GAA) poly-Si transistors

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2002
High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabricated using a novel technique for crystallization of a-Si.
P. Kalavade, K.C. Saraswat
openaire   +1 more source

Two-dimensional confinement effects in gate-all-around (GAA) MOSFETs

Solid-State Electronics, 1998
Two-dimensional electron confinement effects have been modeled and experimentally observed in silicon-on-insulator (SOI) gate-all-around (GAA) MOSFETs. Solving the Poisson and Schrodinger equations in a self-consistent manner provides the electron wave functions and the energy levels within the device channel.
X. Baie, J.P. Colinge
openaire   +1 more source

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