Results 121 to 130 of about 1,279 (182)

Canonical Notch2 signaling regulates development and maintenance of iron-recycling macrophages and iron homeostasis. [PDF]

Nat Commun
Schroth FN, Kapanadze T, Sablotny S, Xu Y, Ascierto A, Ballmaier M, Mauel K, Chung BM, Deuper L, Shaw AS, Kispert A, Lochner M, Kempf T, Mass E, Haller H, Schmidt-Ott KM, Gamrekelashvili J, Limbourg FP.   +17 more
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Design Optimization of Gate-All-Around (GAA) MOSFETs

IEEE Nanotechnology Magazine, 2006
The design of gate-all-around (GAA) MOSFETs was optimized and compared with that of double-gate MOSFETs. We discussed the optimal ratio of the fin width to the gate length and investigated short-channel effects of GAA MOSFETs. Using three-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width ...
Byung-Gook Park, Woo Young Choi, Jae Young Song   +2 more
exaly   +2 more sources

Realization of Gate-All-Around (GAA) SOI MOSFET Using Replacement Gate Mask

2007 IEEE Conference on Electron Devices and Solid-State Circuits, 2007
This paper describes a novel fabrication process of achieving the gate-all-around (GAA) MOSFET device using the replacement gate mask method. In this process, the masking step for the isotropic etch of the bottom gate was replaced by a replacement gate masking step together with a series of processes.
C M Ng
exaly   +2 more sources

AFM characterization for Gate-All-Around (GAA) devices

Metrology, Inspection, and Process Control for Microlithography XXXIV, 2020
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the ...
Mary A. Breton, Jennifer Fullam, Lan Yu, Dexin Kong, Daniel Schmidt, Andrew Greene, Liying Jiang, Sean Hand, Jason Osborne   +8 more
openaire   +1 more source

Characteristics of GaN-Based Nanowire Gate-All-Around (GAA) Transistors

Journal of Nanoscience and Nanotechnology, 2020
We investigate the DC, C–V, and pulse performances in GaN-based nanowire gate-all-around (GAA) transistors with two kinds of geometry: one is AlGaN/GaN heterostructure with two dimensional electron gas (2DEG) channel and the other is only GaN layer without 2DEG channel.
Ki-Sik, Im, Mallem Siva Pratap, Reddy, Jinseok, Choi, Youngmin, Hwang, Jea-Seung, Roh, Sung Jin, An, Jung-Hee, Lee   +6 more
openaire   +2 more sources

Lateral gate-all-around (GAA) poly-Si transistors

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207), 2002
High performance near-single grain poly-Si lateral gate-all-around (GAA) MOS transistors have been demonstrated. A high I/sub ON//I/sub OFF/ ratio of 10/sup 8/ and nearly ideal subthreshold slope of 67 mV/dec were achieved. These devices were fabricated using a novel technique for crystallization of a-Si.
P. Kalavade, K.C. Saraswat
openaire   +1 more source

Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold

Microelectronic Engineering, 1992
Simulations of, drain Current and intrinsic gate capacitances of nMOS/GAA transistors are presented and compared with experimental results. On the basis of the insight they give into the unique behaviour of these devices, new hypotheses have emerged and yielded an analytical model valid around the threshold voltage.
P. Francis, A. Terao, D. Flandre, F. Van de Wiele   +3 more
openaire   +1 more source

ESD characterization of gate-all-around (GAA) Si nanowire devices

2015 IEEE International Electron Devices Meeting (IEDM), 2015
In CMOS scaling roadmap, gate-all-around (GAA) nanowire (NW) is a promising candidate in sub-10nm nodes. However, newly introduced process options in GAA NW technologies can result in significant impacts on intrinsic ESD performance. In this work, ESD protection devices in GAA NW architecture are studied and the corresponding 3D TCAD simulations bring ...
S.-H. Chen, D. Linten, G. Hellings, A. Veloso, M. Scholz, R. Boschke, G. Groeseneken, N. Collaert, A. Thean   +8 more
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Scatterometry for gate all around (GAA) technology enablement (Conference Presentation)

Metrology, Inspection, and Process Control for Microlithography XXXII, 2018
Future of logic silicon extension lies at the heart of gate all around developments (1). Due to the increasing limitations in further FinFET flow extension, teams around the globe are researching with vertical and horizontal nanowires flavors. Horizontal NW are of great interest due to their integration similarity to the existing FinFET integration ...
Anne-Laure Charley, Hans Mertens, Naoto Horiguchi, Philippe Leray, Nivea Figueiró, Matthew Sendelbach, Roy Koret, Avron Ger, Shay Wolfling   +8 more
openaire   +1 more source