Results 141 to 150 of about 1,279 (182)

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

Journal of Computational Electronics, 2018
This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts.
Sarabdeep Singh, Ashish Raman
openaire   +1 more source

Influence of Orientation, Geometry, and Strain on Electron Distribution in Silicon Gate-All-Around (GAA) MOSFETs

IEEE Transactions on Electron Devices, 2011
In this paper, the effects of device orientation, geometry, and strain (uniaxial and biaxial) on the electrostatic properties of different silicon gate-all-around metal-oxide-semiconductor field-effect transistors are thoroughly investigated. We show how the electron density changes with the device orientation and how it depends on the geometry, size ...
Tienda-Luna I.M., Ruiz F.J.G., Godoy A., Biel B., Gamiz F.   +4 more
openaire   +1 more source

(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

ECS Meeting Abstracts, 2019
This paper addresses the opportunities and challenges of wet and dry etches in the integration of gate-all-around (GAA) device, which is emerging as a promising solution to replace FinFET [1-3]. For the GAA device fabrication, a quintessential challenge is an isotropic etching of dielectrics, semiconductors, and metals with high selectivity to the ...
Yusuke Oniki, Efraín Altamirano-Sánchez, Frank Holsteyns   +2 more
openaire   +1 more source

Gate-All-Around (GAA) NWFET with L g = 10 nm Simulation

2017
According to MOSFET scaling rule, the depletion layer formed in the channel of traditional 2D MOSFET near source and drain, the short-channel effect (SCE) has become inevitable along with the scaling of L g dimension.
Yung-Chun Wu, Yi-Ruei Jhan
openaire   +1 more source

Materials characterization for process integration of multi-channel gate all around (GAA) devices

SPIE Proceedings, 2017
Multi-channel gate all around (GAA) semiconductor devices march closer to becoming a reality in production as their maturity in development continues. From this development, an understanding of what physical parameters affecting the device has emerged.
Gangadhara Raja Muthinti, Nicolas Loubet, Robin Chao, Abraham A. de la Peña, Juntao Li, Michael A. Guillorn, Tenko Yamashita, Sivananda Kanakasabapathy, John Gaudiello, Aron J. Cepler, Matthew Sendelbach, Susan Emans, Shay Wolfling, Avron Ger, Daniel Kandel, Roy Koret, Wei Ti Lee, Peter Gin, Kevin Matney, Matthew Wormington   +19 more
openaire   +1 more source

Compact modeling for gate-all-around nanowire tunneling FETs (GAA NW-tFETs)

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012
A compact model for gate-all-around (GAA) nanowire tunneling FETs (NW-tFETs) is developed based on ballistic transport and charge balancing approaches. To account for the carrier injection to the channel from source/drain (S/D) regions for NW FETs, the density-of-states (DOS) charge, which results in the so-called quantum capacitance, is introduced and
Zhiping Yu, Ling Li, Li Zhang, Jinyu Zhang   +3 more
openaire   +1 more source

Significant Performance Enhancement in strained channel GaAs Gate-All-Around (GAA) nanowire

2022 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE), 2022
Dev Desai, Nirmal Lunagariya, Hiral Vasara, Prakash Chandra, Shantanu Agnihotri   +4 more
openaire   +1 more source

SiGe cantilever channel gate-all-around (GAA) fully depleted (FD) PMOSFET with high-¿ and metal gate

2007 65th Annual Device Research Conference, 2007
Scaling the conventional CMOS transistor beyond the 45 nm generation ushers in several fundamental limitations. Control of leakage currents and sustaining electrostatic integrity while maintaining historic enhancements in performance requires such ultra-thin gate-dielectrics and heavily doped bodies that a process window sufficiently large for ...
S.-H. Lee, S. Dey, S V. Joshi, P. Majhi, S.K. Banerjee   +4 more
openaire   +1 more source

Drain current model for a gate all around (GAA) p–n–p–n tunnel FET

Microelectronics Journal, 2013
Abstract A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths.
Rakhi Narang, Manoj Saxena, R. S. Gupta, Mridula Gupta   +3 more
openaire   +2 more sources

Challenges and future scope of gate-all-around (GAA) transistors

2023
Shobhit Srivastava, Abhishek Acharya
openaire   +1 more source