Results 71 to 80 of about 1,221 (182)

Performance investigation of 1T1R memory cell using GAA MBC-FET technology

Memories - Materials, Devices, Circuits and Systems
The ultimate advancement beyond FinFET technology is the Gate-All-Around (GAA) Multi-Bridge-Channel FET (MBCFET) technology. GAA MBCFET features vertically stacked multiple channels, a departure from single-channel designs, thereby enhancing overall ...
Rinku Rani Das, Devenderpal Singh, Alex James   +2 more
doaj   +1 more source

Low-Power Energy-Efficient Hetero-Dielectric Gate-All-Around MOSFETs: Enablers for Sustainable Smart City Technology

Energies
In the context of increasing digitalization and the emergence of applications such as smart cities, embedded devices are becoming ever more pervasive, mobile, and ubiquitous.
Ram Devi, Gurpurneet Kaur, Ameeta Seehra, Munish Rattan, Geetika Aggarwal, Michael Short   +5 more
doaj   +1 more source

A Compact Model for Program Operation of Gate-All-Around Barrier-Engineered Charge-Trapping NAND Flash Memory in the FN-Tunneling Regime

IEEE Journal of the Electron Devices Society
We introduce a compact model for characterizing the transient program operation of Gate-All-Around (GAA) Barrier-Engineered charge-trapping NAND flash (BE-CTNF) memory, especially in the FN-tunneling regime.
Haechan Choi, Hyungcheol Shin
doaj   +1 more source

Performance Study and Analysis of Heterojunction Gate All Around Nanowire Tunneling Field Effect Transistor [PDF]

Journal of Optoelectronical Nanostructures, 2019
In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details.
Mahsa Roohy, Reza Hosseini
doaj  

Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

IEEE Journal of the Electron Devices Society
Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect ...
Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh   +5 more
doaj   +1 more source

Analytical subthreshold swing model of junctionless elliptic gate-all-around (GAA) FET

AIMS Electronics and Electrical Engineering
<p>An analytical subthreshold swing (SS) model has been presented to determine the SS of an elliptic junctionless gate-all-around field-effect transistor (GAA FET). The analysis of a GAA FET with an elliptic cross-section is essential because it is difficult to manufacture a GAA FET with an accurate circular cross-section during the process.
openaire   +2 more sources

3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography. [PDF]

Nat Commun
Karapetyan S, Zeltmann SE, Wilk G, Chen TK, Hou VD, Muller DA.   +5 more
europepmc   +1 more source

3D Nanoscale Imaging of Semiconductor Films for GAA (Gate All Around) Device Development

Microscopy and Microanalysis, 2022
Pritesh Parikh, Darshan Jaware, Jiangtao Zhu   +2 more
openaire   +1 more source

Scaling nanoribbon transistors with monolayer transition metal dichalcogenides. [PDF]

Nat Nanotechnol
Peña T, Persson AEO, Krayev A, Friðriksdóttir Á, Su H, Lee YM, Song YS, Neilson K, Zhang Z, Hoang AT, Yang JA, Hoang L, Wang SX, Mannix AJ, McIntyre PC, Pop E.   +15 more
europepmc   +1 more source

Large-scale gate-all-around MoS₂ transistor array through lossless monolithic 3D integration. [PDF]

Natl Sci Rev
Chen C, Chen K, Zhao H, Lu S, Shang J, Jiang H, Gao L, He X, Jiang S, Chen Z, Zhang Z, Zhang X, Zhang Y.   +12 more
europepmc   +1 more source