N-Type Nanosheet FETs without Ground Plane Region for Process Simplification. [PDF]
Lee KS, Park JY.
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SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview. [PDF]
Gul W, Shams M, Al-Khalili D.
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Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices. [PDF]
Zhang Q +19 more
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Remote Plasma Selective Silicon Etching Enabled Tunable Sub-Fin Process for Improved Parasitic Bottom Channel Control in Gate-All-Around Nanosheet Field-Effect Transistors. [PDF]
Li J, Gao Y, Zhang DW.
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application/pdf 学術論文 (Article) 294853 ...
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Suppression of Short-Channel Effects in AlGaN/GaN HEMTs Using SiNx Stress-Engineered Technique. [PDF]
Deng C +10 more
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Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter. [PDF]
Wang B +5 more
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Simultaneously Estimating Process Variation Effect, Work Function Fluctuation, and Random Dopant Fluctuation of Gate-All-Around Silicon Nanosheet Complementary Field-Effect Transistors. [PDF]
Kola SR, Li Y.
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Random Telegraph Noises from the Source Follower, the Photodiode Dark Current, and the Gate-Induced Sense Node Leakage in CMOS Image Sensors. [PDF]
Chao CY +8 more
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Ultralow-power LSI Technology with Silicon on Thin Buried Oxide (SOTB) CMOSFET [PDF]
Nobuyuki Sugii +4 more
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