Results 121 to 130 of about 2,685 (171)
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2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), 2022
In this work we have proposed and examined a novel Macaroni Channel-Nanowire Field Effect Transistor (MCNW-FET) for Gate-Induced Drain Leakage (GIDL) reduction applications. MC-NW-FET is compared with a conventional nanowire device (NW-FET).
Aapurva Kaul, Sonam Rewari, Deva Nand
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In this work we have proposed and examined a novel Macaroni Channel-Nanowire Field Effect Transistor (MCNW-FET) for Gate-Induced Drain Leakage (GIDL) reduction applications. MC-NW-FET is compared with a conventional nanowire device (NW-FET).
Aapurva Kaul, Sonam Rewari, Deva Nand
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Simulation of amplified gate-induced-drain-leakage (GIDL) in short-channel SOI MOSFETs
Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V, 2002Amplification of gate-induced-drain-leakage current has been reported for short channel MOS-transistors on SOI substrate. Here, we show that this effect is reproduced consistently by 2D-device simulation when a band-to-band tunneling model is included.
A. von Schwerin, W. Bergner, K. Jacobs
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IEEE Transactions on Electron Devices, 2009
In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application.
Shian-Jyh Lin +9 more
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In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application.
Shian-Jyh Lin +9 more
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IEEE Electron Device Letters, 2009
A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized ...
Han, JW Han, Jin-Woo +3 more
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A soft-programming-free operation method in unified RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized ...
Han, JW Han, Jin-Woo +3 more
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2008 IEEE Silicon Nanoelectronics Workshop, 2008
A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher ...
Han Ki Chung +9 more
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A capacitor-less one-transistor DRAM cell with surrounding gate MOSFET with vertical channel (SGVC) using gate-induced drain leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact ionization current, the write operation with GIDL current provides high sensing margin owing to higher ...
Han Ki Chung +9 more
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IEEE Transactions on Electron Devices, 2006
A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude ...
E. Yoshida, T. Tanaka
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A capacitorless one-transistor (1T)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation was demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude ...
E. Yoshida, T. Tanaka
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Solid-State Electronics, 2009
Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling.
null Seongjae Cho +5 more
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Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling.
null Seongjae Cho +5 more
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IEEE Electron Device Letters, 1992
An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices.
J. Chen, F. Assaderaghi, P.-K. Ko, C. Hu
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An off-state leakage current unique for short-channel SOI MOSFETs is reported. This off-state leakage is the amplification of gate-induced-drain-leakage current by the lateral bipolar transistor in an SOI device due to the floating body. The leakage current can be enhanced by as much as 100 times for 1/4 mu m SOI devices.
J. Chen, F. Assaderaghi, P.-K. Ko, C. Hu
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2009 IEEE International Memory Workshop, 2009
A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time.
Puget, S. +9 more
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A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time.
Puget, S. +9 more
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IEEE International Electron Devices Meeting 2003, 2004
A capacitorless 1T DRAM cell using gate-induced drain leakage (GIRL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for
E. Yoshida, T. Tanaka
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A capacitorless 1T DRAM cell using gate-induced drain leakage (GIRL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for
E. Yoshida, T. Tanaka
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