S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s
IEEE Access, 2021 In this paper, we compare conventional saddle type FinFETs to partial isolation type saddle FinFETs (Pi-FinFETs) using 3D TCAD simulations to examine the effect of single charge traps for proper prediction of leakage current.
Jin Hyo Park +5 more
doaj +1 more source
Analysis of total dose-induced dark current in CMOS image sensors from interface state and trapped charge density measurements [PDF]
, 2010 The origin of total ionizing dose induced dark current in CMOS image sensors is investigated by comparing dark current measurements to interface state density and trapped charge density measurements.
Girard, Sylvain +4 more
core +4 more sources
Simulation of Graphene Nanoribbon Field Effect Transistors [PDF]
, 2007 We present an atomistic three-dimensional simulation of graphene nanoribbon field effect transistors (GNR-FETs), based on the self-consistent solution of the 3D Poisson and Schroedinger equation with open boundary conditions within the non-equilibrium ...
Fiori, G., Iannaccone, G.
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Accurate leakage current models for MOSFET nanoscale devices [PDF]
, 2020 This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage ...
Mistarihi, Mamoun +2 more
core +3 more sources
Improved drive current in RF vertical MOSFETS using hydrogen anneal [PDF]
, 2011 This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications.
Abuelgasim, A. +6 more
core +1 more source
Total dose evaluation of deep submicron CMOS imaging technology through elementary device and pixel array behavior analysis [PDF]
, 2008 Ionizing radiation effects on CMOS image sensors (CIS) manufactured using a 0.18 µm imaging technology are presented through the behavior analysis of elementary structures, such as field oxide FET, gated diodes, photodiodes and MOSFETs.
Bernard, Frédéric +4 more
core +2 more sources
Extensionless UTBB FDSOI Devices in Enhanced Dynamic Threshold Mode under Low Power Point of View
Journal of Low Power Electronics and Applications, 2015 This work presents an analysis about the influence of the gate and source/drain underlap length (LUL) on UTBB FDSOI (UltraThin-Body-and-Buried-oxide Fully-Depleted-Silicon-On-Insulator) devices operating in conventional (VB = 0 V), dynamic threshold (DT,
Katia Regina Akemi Sasaki +4 more
doaj +1 more source
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study
IEEE Access, 2020 The leakage mechanisms of inefficient volume depletion and lateral band to band tunneling (L-BTBT) restrict the scaling of SOI-junctionless (JL) FETs. Therefore, in this article, we investigate the scalability of the SOI-JLFETs by incorporating a ground ...
Aakash Kumar Jain +1 more
doaj +1 more source
Adaptive differential amplitude pulse-position modulation technique (DAPPM) using fuzzy logic for optical wireless communication channels [PDF]
, 2012 In the past few years, people have become increasingly demanding for high transmission rate, using high-speed data transfer rate, the number of user increased every year, therefore the high-speed optical wireless communication link have become more
Bong, Siaw Wee
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Surface Potential-Based Polycrystalline-Silicon Thin-Film Transistors Compact Model by Nonequilibrium Approach [PDF]
, 2013 We propose a surface potential-based polycrystalline silicon thin-film transistors (poly-Si TFTs) compact model considering a nonequilibrium state. A drain current model considers grain boundary (GB) trap-related physical phenomena: composite mobility of
Ikeda H., Sano N., 佐野 伸行
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