Results 41 to 50 of about 2,685 (171)

Electrically detected magnetic resonance of ion-implantation damage centers in silicon large-scale integrated circuits [PDF]

, 2003
We used electrically detected magnetic resonance to study the microscopic structure of ion-implantation-induced point defects that remained in large-scale Si integrated circuits (Si LSIs).
Hamada K., Mochizuki Y., Okonogi K., Umeda T., 梅田 享英   +4 more
core   +1 more source

Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

, 2006
Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations.
Ashburn, P., de Groot, C.H., Gili, E., Hakim, M.M.A., Hall, S., Kunz, D., Uchino, T.   +6 more
core   +1 more source

Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD‐SOI MOSFETs

Active and Passive Electronic Components, Volume 2015, Issue 1, 2015., 2015
TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and ...
A. Ciprut, A. Chelly, A. Karsenty, Gerard Ghibaudo   +3 more
wiley   +1 more source

An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

IEEE Journal of the Electron Devices Society, 2018
This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance ...
Min Hee Cho, Namho Jeon, Taek Yong Kim, Moonyoung Jeong, Sungsam Lee, Jong Seo Hong, Hyeong Sun Hong, Satoru Yamada   +7 more
doaj   +1 more source

FinFETs: From Devices to Architectures

Advances in Electronics, Volume 2014, Issue 1, 2014., 2014
Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short‐channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology ...
Debajit Bhattacharya, Niraj K. Jha, Jaber Abu Qahouq   +2 more
wiley   +1 more source

In Materia Shaping of Randomness with a Standard Complementary Metal‐Oxide‐Semiconductor Transistor for Task‐Adaptive Entropy Generation

Advanced Functional Materials, EarlyView.
This study establishes a materials‐driven framework for entropy generation within standard CMOS technology. By electrically rebalancing gate‐oxide traps and Si‐channel defects in foundry‐fabricated FDSOI transistors, the work realizes in‐materia control of temporal correlation – achieving task adaptive entropy optimization for reinforcement learning ...
Been Kwak, Ryun‐Han Koo, Youngchan Cho, Changhyeon Han, Dongbin Kim, Soi Jeong, Yunho Shin, Joonhyeok Choi, Jiseong Im, Jonghyun Ko, Jong‐Ho Lee, Jangsaeng Kim, Youngho Kang, Wonjun Shin, Daewoong Kwon   +14 more
wiley   +1 more source

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate‐Recessed Nanoscale SOI MOSFETs

Active and Passive Electronic Components, Volume 2013, Issue 1, 2013., 2013
Ultrathin body (UTB) and nanoscale body (NSB) SOI‐MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate‐recessed” process on the same silicon wafer. Their current‐voltage characteristics measured at room temperature were found to be surprisingly different ...
A. Karsenty, A. Chelly, Gerard Ghibaudo
wiley   +1 more source

Advancement in Nanoscale CMOS Device Design En Route to Ultra‐Low‐Power Applications

VLSI Design, Volume 2011, Issue 1, 2011., 2011
In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery‐operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low‐power and ultra‐low‐power consumption in various applications.
Subhra Dhar, Manisha Pattanaik, Poolla Rajaram, A. G. M. Strollo   +3 more
wiley   +1 more source

Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash

IEEE Access
We propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim, Jiwook Hong, Moonchurl Kim, Hyoungsub Kim, Jongwook Jeon   +4 more
doaj   +1 more source

1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning

Advanced Intelligent Systems, Volume 7, Issue 8, August 2025.
This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge ...
MD Yasir Bashir, Pritish Sharma, Shubham Sahay   +2 more
wiley   +1 more source