Results 61 to 70 of about 2,685 (171)
Impact of Work-Function Variation in Ferroelectric Field-Effect Transistor
IEEE Journal of the Electron Devices SocietyWe analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE)
Su Yeon Jung +3 more
doaj +1 more source
The Potential and the Drawbacks of Underlap Single-Gate Ultrathin SOI MOSFET [PDF]
, 2008 This paper describes the performance prospect of underlapped single-gate ultra-thin (USU) SOI MOSFET with a low-k or high-k gate dielectric from the viewpoint of both digital and analog applications.
Hamada Mitsuo +4 more
core +1 more source
Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM
IEEE AccessThis study investigates the row hammer tolerance and potential degradation by capacitive crosstalk (CC) and parasitic bipolar junction transistor (BJT) effect in vertically stacked dynamic random-access memory (VS-DRAM) using technology computer-aided ...
Minki Suh +7 more
doaj +1 more source
SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Applied SciencesThree-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
doaj +1 more source
Design Strategies for Ultralow Power 10nm FinFETs [PDF]
, 2017 Integrated circuits and microprocessor chips have become integral part of our everyday life to such an extent that it is difficult to imagine a system related to consumer electronics, health care, public transportation, household application without ...
Walke, Abhijeet M
core +2 more sources
Device Characterization of 0.8-µm CMOS Technology [PDF]
, 2000 The development of the O.8-um CMOS technology was carried out in Mimos Berhad and is considered to be the first in-house development to be done in Malaysia.
Kooh, Roy Jinn Chye
core
IEEE AccessIn this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj +1 more source
High field induced stress suppression of GIDL effects in TFTs [PDF]
, 2010 Gate-Induced drain leakage (GIDL) is an unwanted short-channel effect that occurs at higher drain biases in an overdriven off state of a transistor. The GIDL is the result of a deep depletion region that forms in the drain at high drain-to-gate biases ...
McCabe, Andrew
core +1 more source
The Impact of Gate-Induced Drain Leakage (GIDL) on Scaled MOSFETs for Low Power Device [PDF]
, 2018 In this research, we investigated the impact of Gate-Induced Drain Leakage (GIDL) on scaled Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) for low power application.
AH, AM +6 more
core +1 more source
GIDL characteristics on Si1-xGex pFinFET for Low Power Transistors [PDF]
, 2016 학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 2. 신형철.This dissertation presents an investigation of Gate-Induced-Drain-Leakage (GIDL) current in SiliconGermanium (SiGe) p-type FinFET for low power transistors and proposes the guidelines to reduce GIDL current.
강덕승
core