Results 141 to 150 of about 1,624 (169)
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Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire
2020In this paper, detailed gate-induced drain leakage (GIDL) mechanism is analyzed in conventional nano-wire. It has been seen that conventional nano-wire suffers from both lateral and transversal band-to-band tunneling. The lateral component tunneling is more severe and active when device is in OFF condition.
Abhishek Kumar +2 more
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Greatly suppressed stress-induced shift of GIDL in N2O-based n-MOSFET's
Solid-State Electronics, 1998Abstract Considerably suppressed gate-induced drain leakage (GIDL) shifts of N 2 O-based n-MOSFET's after hot-carrier stress with different gate voltages are observed. The mechanisms involved are studied by dividing gate-oxide traps into sub-interface and bulk-oxide traps, and by means of computer simulations on electric-field distribution and ...
Huang, L +4 more
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Effect of substrate negative bias on GIDL current in LDD nMOSFET's
2011 International Conference on Mechatronic Science, Electric Engineering and Computer (MEC), 2011The effect of substrate negative bias V B on the gate-induced drain leakage (GIDL) current is studied. It is found that the negative V B leads GIDL current curve shifts upwards. The shift of GIDL current ΔI D /I D increases with increasing |V B |. The GIDL current at V G =−0.2V (in the low field region) increases with increasing |V B | more largely ...
Chen Haifeng, Du Huimin, Guo Lixin
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Anomalous GIDL Effect With Back Bias in FinFET: Physical Insights and Compact Modeling
IEEE Transactions on Electron Devices, 2021In this work, we report a detailed study and modeling of bulk current in the low forward bias region. In the forward bias region, the bulk current shows a gate-induced drain leakage (GIDL) such as strong modulation with gate voltage although from the band alignment one would not expect any tunneling current.
Chetan Kumar Dabhi +3 more
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Decoupled tunneling and GIDL effects for 28nm high-k stacked nMOSFETs
2017 6th International Symposium on Next Generation Electronics (ISNE), 2017One interesting result for 28nm high-k stacked n-channel MOSFET with W/L= 0.5/0.12 (μm/μm) electrically sensed demonstrates the tunneling and GIDL effects which can effectively be decoupled by gate bias at accumulation mode. Due to the drain bias assisted, the decoupling performance in this work is more apparent.
null Mu-Chun Wang +5 more
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A GIDL-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2
2007 International Conference on Communications, Circuits and Systems, 2007A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs has been proposed and implemented into HiSIM2, first complete surface potential based model. The model consists of one tunneling mechanism considering two tunneling currents, band to band tunneling (BTBT) and trap assisted tunneling (TAT), and requires totally 7 model parameters ...
R. Inagaki, M. Miura-Mattausch, Y. Inoue
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A New Tunnelling Model To Calculate GIDL Current For MOSFET And TFET
2019 International Semiconductor Conference (CAS), 2019This paper has proposed an innovative band to band tunneling current model using De- Casteljau’s algorithm, followed by Bezier curve method and WKB approximation. After verifying the validity of this proposed tunneling model with respect to electron energy and tunnel width, the expression of tunneling probability is applied to the graded drain MOSFET ...
A. Sen, J. Das
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Impact of Hot Carrier Degradation on GIDL Current in 45nm SOI-NFETs
2019 IEEE International Integrated Reliability Workshop (IIRW), 2019The impact of hot-carrier stress on the device performance parameters such as ON-current, threshold voltage and transconductance has been studied extensively in the literature. However, limited work highlighting the impact on OFF-state performance is available.
Charu Gupta, Anshul Gupta, Abhisek Dixit
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Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM
2016 IEEE 8th International Memory Workshop (IMW), 2016A novel work-function modulation technique for dual work-function (WF) metal gate for DRAM access device is investigated to minimize the leakage current in the access transistor. Gate Induced Drain Leakage (GIDL) is believed to be the most dominant off state leakage from storage node junction.
S. K. Gautam +5 more
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Temperature influence on UTBOX 1T-DRAM using GIDL for writing operation
2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), 2012This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations.
K. R. A. Sasaki +5 more
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