Results 121 to 130 of about 445 (155)

Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs

IEEE Electron Device Letters, 2009
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the off state. However, our experimental results reveal that the capacitance
null Chia-Sheng Lin, null Ying-Chung Chen, null Ting-Chang Chang, null Shih-Ching Chen, null Fu-Yen Jian, null Hung-Wei Li, null Te-Chih Chen, null Chi-Feng Weng, null Jin Lu, null Wei-Che Hsu   +9 more
openaire   +1 more source

A GIDL-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

2007 International Conference on Communications, Circuits and Systems, 2007
A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs has been proposed and implemented into HiSIM2, first complete surface potential based model. The model consists of one tunneling mechanism considering two tunneling currents, band to band tunneling (BTBT) and trap assisted tunneling (TAT), and requires totally 7 model parameters ...
R. Inagaki, M. Miura-Mattausch, Y. Inoue
openaire   +1 more source

Anomalous GIDL Effect With Back Bias in FinFET: Physical Insights and Compact Modeling

IEEE Transactions on Electron Devices, 2021
In this work, we report a detailed study and modeling of bulk current in the low forward bias region. In the forward bias region, the bulk current shows a gate-induced drain leakage (GIDL) such as strong modulation with gate voltage although from the band alignment one would not expect any tunneling current.
Chetan Kumar Dabhi, Ananda S. Roy, Lucy Yang, Yogesh Singh Chauhan   +3 more
openaire   +1 more source

Impact of Hot Carrier Degradation on GIDL Current in 45nm SOI-NFETs

2019 IEEE International Integrated Reliability Workshop (IIRW), 2019
The impact of hot-carrier stress on the device performance parameters such as ON-current, threshold voltage and transconductance has been studied extensively in the literature. However, limited work highlighting the impact on OFF-state performance is available.
Charu Gupta, Anshul Gupta, Abhisek Dixit
openaire   +1 more source

Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM

2016 IEEE 8th International Memory Workshop (IMW), 2016
A novel work-function modulation technique for dual work-function (WF) metal gate for DRAM access device is investigated to minimize the leakage current in the access transistor. Gate Induced Drain Leakage (GIDL) is believed to be the most dominant off state leakage from storage node junction.
S. K. Gautam, S. Maheshwaram, S. K. Manhas, Arvind Kumar, Steven Sherman, Sung Ho Jo   +5 more
openaire   +1 more source

Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Standby power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher.
Suyoung Bang, David T. Blaauw, Dennis Sylvester, Massimo Alioto   +3 more
openaire   +1 more source

Decoupled tunneling and GIDL effects for 28nm high-k stacked nMOSFETs

2017 6th International Symposium on Next Generation Electronics (ISNE), 2017
One interesting result for 28nm high-k stacked n-channel MOSFET with W/L= 0.5/0.12 (μm/μm) electrically sensed demonstrates the tunneling and GIDL effects which can effectively be decoupled by gate bias at accumulation mode. Due to the drain bias assisted, the decoupling performance in this work is more apparent.
null Mu-Chun Wang, null Ko-Chin Hsu, null Jin-Wei Guo, null Heng-Sheng Huang, null Shuang-Yuan Chen, null Shea-Jue Wang   +5 more
openaire   +1 more source

An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET

IEEE Transactions on Electron Devices, 2001
An analytic three-terminal band-to-band tunneling current model for the gate-induced drain leakage current (GIDL) in an n-MOSFET is developed. This model considers impurity doping concentration, vertical field, lateral field, and so-induced electron momentum enhancement, as well as the surface electro-static potential in the gate-to-drain overlapped ...
null Ja-Hao Chen, null Shyh-Chyi Wong, null Yeong-Her Wang   +2 more
openaire   +1 more source

Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire

2020
In this paper, detailed gate-induced drain leakage (GIDL) mechanism is analyzed in conventional nano-wire. It has been seen that conventional nano-wire suffers from both lateral and transversal band-to-band tunneling. The lateral component tunneling is more severe and active when device is in OFF condition.
Abhishek Kumar, Sushmita Jaiswal, Santosh Kumar Gupta   +2 more
openaire   +1 more source

Temperature influence on UTBOX 1T-DRAM using GIDL for writing operation

2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), 2012
This paper investigates the temperature influence on Ultra Thin Buried Oxide (UTBOX) FDSOI devices used as a 1T-DRAM (single transistor dynamic random access memory cell) using GIDL (Gate Induced Drain Leakage) for writing operation through numerical simulations.
K. R. A. Sasaki, L. M. Almeida, J A. Martino, M. Aoulaiche, E. Simoen, C. Claeys   +5 more
openaire   +1 more source