Results 101 to 110 of about 354 (151)

Decoupled tunneling and GIDL effects for 28nm high-k stacked nMOSFETs

2017 6th International Symposium on Next Generation Electronics (ISNE), 2017
One interesting result for 28nm high-k stacked n-channel MOSFET with W/L= 0.5/0.12 (μm/μm) electrically sensed demonstrates the tunneling and GIDL effects which can effectively be decoupled by gate bias at accumulation mode. Due to the drain bias assisted, the decoupling performance in this work is more apparent.
Mu-Chun Wang, Shea-Jue Wang
exaly   +2 more sources

Gate-Induced-Drain-Leakage (GIDL) in CMOS Enhanced by Mechanical Stress

IEEE Transactions on Electron Devices, 2022
Anastasiia Kruv, Ben Kaczer, Kookjin Lee   +2 more
exaly   +2 more sources

Investigation of the characteristics of GIDL current in 90nm CMOS technology

Chinese Physics, 2006
A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain–gate voltage VDG.
Chen Hai-Feng, Hao Yue, Ma Xiao-Hua, Zhang Jin-Cheng, Li Kang, Cao Yan-Rong, Zhang Jin-Feng, Zhou Peng-Ju   +7 more
openaire   +2 more sources

Effects of X-ray irradiation on GIDL in MOSFETs

IEEE Electron Device Letters, 1992
The effect of X-ray irradiation on the gate-induced drain leakage (GIDL) is shown to be mostly due to the electrostatic effect of the trapped positive charge in n-channel MOSFETs. In p-channel MOSFETs, in addition, irradiation increases the interface-state-assisted tunneling component of the GIDL.
A. Acovic, C.C.-H. Hsu, L.-C. Hsia, A. Balasinski, T.-P. Ma   +4 more
openaire   +1 more source

PMOSFET anti-fuse using GIDL-induced-HEIP mechanism

Microelectronics Reliability, 2010
Abstract We propose a novel electrical fuse (e-fuse) program procedure using shallow trench isolation (STI) edge trapping mechanism of PMOSFET by applying AC pulses. We obtained flash characteristics using conventional PMOSFET structure, when injected AC pulse on source node under off-state condition (Vg = high, Vd = low).
J. Y. Seo, J. E. Seok, W. S. Kim, N. H. Cha, J. S. Kang, B. S. So   +5 more
openaire   +1 more source

Approximations to field-effect factor and their use in GIDL modeling

18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2011
New analytical approximations to field-effect factor used in gate induced drain leakage (GIDL) current modeling are presented. Modeling results for GIDL currents in sphere-shaped recessed channel array transistor (SRCAT) and NMOSFET obtained with the use of new approximations were compared to the measurement data in order to prove the validity of the ...
Nikita Kozhukhov, null Byoungchan Oh, null Hyungcheol Shin   +2 more
openaire   +1 more source

A New Tunnelling Model To Calculate GIDL Current For MOSFET And TFET

2019 International Semiconductor Conference (CAS), 2019
This paper has proposed an innovative band to band tunneling current model using De- Casteljau’s algorithm, followed by Bezier curve method and WKB approximation. After verifying the validity of this proposed tunneling model with respect to electron energy and tunnel width, the expression of tunneling probability is applied to the graded drain MOSFET ...
A. Sen, J. Das
openaire   +1 more source

Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs

IEEE Electron Device Letters, 2009
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the off state. However, our experimental results reveal that the capacitance
null Chia-Sheng Lin, null Ying-Chung Chen, null Ting-Chang Chang, null Shih-Ching Chen, null Fu-Yen Jian, null Hung-Wei Li, null Te-Chih Chen, null Chi-Feng Weng, null Jin Lu, null Wei-Che Hsu   +9 more
openaire   +1 more source

GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications

IEEE Electron Device Letters, 2013
Investigation of gate-induced drain leakage (GIDL) in thick-oxide dual-gate doped- and undoped-channel FinFET devices through 3-D process and device simulations is presented. For a given gate length (LG) and gate dielectric thickness, the placement and grading of the drain junction and the channel doping are shown to have a tremendous impact on GIDL ...
Pranita Kerber, Qintao Zhang, Siyuranga Koswatta, Andres Bryant   +3 more
openaire   +1 more source

Impact of substrate bias on GIDL for thin-BOX ETSOI devices

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011
We present a detailed analysis of substrate bias (V bb ) impact on gate induced drain leakage (GIDL) for thin-BOX extremely thin silicon-on-insulator (ETSOI) with BOX thickness (T BOX ) ranging from 10 to 50 nm and inversion layer thicknesses (T INV ) ranging from 1.1 to 1.3 nm.
P. Kulkarni, Q. Liu, A. Khakifirooz, Y. Zhang, K. Cheng, F. Monsieur, P. Oldiges   +6 more
openaire   +1 more source