Results 91 to 100 of about 445 (155)

Point mémoire analogique basse tension basé sur l'effet GIDL

, 2004
La mémoire est un élément incontournable de tout circuit électronique; le développement des applications analogiques basse puissance et basse tension sera conditionné par la disponibilité de points mémoire présentant ces mêmes caractéristiques.
Butaye, Olivier, Donckers, Nicolas, Flandre, Denis, TAISA 2004 - 5ème Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications, Verleysen, Michel   +4 more
core  

Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer Technology

, 2018
We propose a novel optimized design strategy by considering the correlated effects of high-kappa gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure.
Jeong, Jae Won, Shin, Sunhae, Kim, Kyung Rok, Jang, Esan   +3 more
core   +1 more source

Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

, 2006
Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations.
Ashburn, P., Gili, E., Kunz, D., Hakim, M.M.A., Uchino, T., Hall, S., de Groot, C.H.   +6 more
core  

Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

, 2015
In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies.
Li, Ming, Xuan, Haoran, Xu, Xiaoyan, Yang, Yuancheng, Fan, Jiewen, Huang, Ru   +5 more
core   +1 more source

Analisi delle dinamiche di stringa indotte da GIDL in matrici di memoria NAND Flash 3D

, 2017
LAUREA MAGISTRALEIn questo lavoro di tesi saranno studiate le dinamiche di stringa indotte da GIDL al selettore in matrici di memoria NAND Flash 3D a canale verticale.
MALAVENA, GERARDO
core  

3나노 노드 소자에서 기들 측면의 스페이서 최적화 [PDF]

, 2019
학위논문(석사)--서울대학교 대학원 :공과대학 전기·정보공학부,2019. 8. 신형철.본 논문에서는 오프 상태 누설 전류의 관점에서 게이트 측벽 스페이서의 구조 및 물질 최적화를 3nm 노드 나노 플레이트 소자에서 수행했다. 첫째, 게이트 누설 전류의 주 요인 인 기들 (GIDL) 전류와 능동 성능 (온 전류, 온 / 오프 전류 비)가 게이트 측벽 스페이서와 게이트 및 소스.드레인과의 구조적 상관 관계에 따라 공동 최적화되었다.
류동현
core  

Simulation Study on the Role of GIDL Current for Erase Operation in FeFETs

JSAP Annual Meetings Extended Abstracts, 2021
Mei, Xiaoran, Mo, Fei, Hiramoto, Toshiro, Kobayashi, Masaharu   +3 more
openaire   +1 more source

A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs

, 2009
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry,
Benson, James
core  

Gidl, Anneliese, Alpenverein. Die Städter entdecken die Alpen [PDF]

Revue de l’Institut français d’histoire en Allemagne, 2013
openaire   +1 more source

A residual-based deep learning approach for ghost imaging.

Ghost imaging using deep learning (GIDL) is a kind of computational quantum imaging method devised to improve the imaging efficiency. However, among most proposals of GIDL so far, the same set of random patterns were used in both the training and test ...

core   +1 more source