Results 111 to 120 of about 347 (149)

Impact of substrate bias on GIDL for thin-BOX ETSOI devices

2011 International Conference on Simulation of Semiconductor Processes and Devices, 2011
We present a detailed analysis of substrate bias (V bb ) impact on gate induced drain leakage (GIDL) for thin-BOX extremely thin silicon-on-insulator (ETSOI) with BOX thickness (T BOX ) ranging from 10 to 50 nm and inversion layer thicknesses (T INV ) ranging from 1.1 to 1.3 nm.
P. Kulkarni, Q. Liu, A. Khakifirooz, Y. Zhang, K. Cheng, F. Monsieur, P. Oldiges   +6 more
openaire   +1 more source

GIDL effect observed in FinFET shapes and Vt implant energy

2018 7th International Symposium on Next Generation Electronics (ISNE), 2018
The leakage of FinFETs with the different features and V t implant energy is observed and strongly related to the previous factors. Due to the process controllability, especially in photo-lithography, the multi-channel shape to promote the drive current seems not easy to be controlled well and deteriorates the desired target.
Ting-Wei Chao, Tien-Szu Shen, Chii-Ruey Lin, Ching-Chuan Chou, Chia-Hsien Chang, Wen-Shiang Liao, Mu-Chun Wang   +6 more
openaire   +1 more source

Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs

IEEE Electron Device Letters, 2009
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the off state. However, our experimental results reveal that the capacitance
null Chia-Sheng Lin, null Ying-Chung Chen, null Ting-Chang Chang, null Shih-Ching Chen, null Fu-Yen Jian, null Hung-Wei Li, null Te-Chih Chen, null Chi-Feng Weng, null Jin Lu, null Wei-Che Hsu   +9 more
openaire   +1 more source

A GIDL-Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

2007 International Conference on Communications, Circuits and Systems, 2007
A GIDL (Gate Induced Drain Leakage) current model for advanced MOSFETs has been proposed and implemented into HiSIM2, first complete surface potential based model. The model consists of one tunneling mechanism considering two tunneling currents, band to band tunneling (BTBT) and trap assisted tunneling (TAT), and requires totally 7 model parameters ...
R. Inagaki, M. Miura-Mattausch, Y. Inoue
openaire   +1 more source

Greatly suppressed stress-induced shift of GIDL in N2O-based n-MOSFET's

Solid-State Electronics, 1998
Abstract Considerably suppressed gate-induced drain leakage (GIDL) shifts of N 2 O-based n-MOSFET's after hot-carrier stress with different gate voltages are observed. The mechanisms involved are studied by dividing gate-oxide traps into sub-interface and bulk-oxide traps, and by means of computer simulations on electric-field distribution and ...
Huang, L, Lo, HB, Lai, PT, Cheng, YC, Xu, JP   +4 more
openaire   +2 more sources

Impact of Hot Carrier Degradation on GIDL Current in 45nm SOI-NFETs

2019 IEEE International Integrated Reliability Workshop (IIRW), 2019
The impact of hot-carrier stress on the device performance parameters such as ON-current, threshold voltage and transconductance has been studied extensively in the literature. However, limited work highlighting the impact on OFF-state performance is available.
Charu Gupta, Anshul Gupta, Abhisek Dixit
openaire   +1 more source

Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM

2016 IEEE 8th International Memory Workshop (IMW), 2016
A novel work-function modulation technique for dual work-function (WF) metal gate for DRAM access device is investigated to minimize the leakage current in the access transistor. Gate Induced Drain Leakage (GIDL) is believed to be the most dominant off state leakage from storage node junction.
S. K. Gautam, S. Maheshwaram, S. K. Manhas, Arvind Kumar, Steven Sherman, Sung Ho Jo   +5 more
openaire   +1 more source

Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011
In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current.
Xu, C., Batude, P., Romanjek, K., Le Royer, C., Tabone, C., Previtali, B., Jaud, M-A., Garros, X., Vinet, M., Poiroux, T., Rafhay, Quentin, Mouis, M.   +11 more
openaire   +2 more sources

Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Standby power reduction is critical to battery life and volume reduction in mm-scale sensor nodes. Power gating is extensively adopted to reduce leakage, but the inserted sleep transistors can suffer from other leakage mechanisms, namely GIDL, which become dominant at battery voltages of 3 V or higher.
Suyoung Bang, David T. Blaauw, Dennis Sylvester, Massimo Alioto   +3 more
openaire   +1 more source

Controlling GIDL Using Core–Shell Technique in Conventional Nano-Wire

2020
In this paper, detailed gate-induced drain leakage (GIDL) mechanism is analyzed in conventional nano-wire. It has been seen that conventional nano-wire suffers from both lateral and transversal band-to-band tunneling. The lateral component tunneling is more severe and active when device is in OFF condition.
Abhishek Kumar, Sushmita Jaiswal, Santosh Kumar Gupta   +2 more
openaire   +1 more source