Results 71 to 80 of about 445 (155)

New observation and improvement in GIDL of n-MOSFETs with various kinds of N2O-based gate oxides under hot-carrier stress

, 1996
Degradation in gate-induced drain leakage (GIDL) of n-MOSFETs with various kinds of gate oxides under hot-carrier stress at different gate voltages is investigated. It has been found that the shift of GIDL current is very sensitive to gate voltage and is
Xu, J, Lai, PT, Zeng, X, Cheng, YC
core   +1 more source

Synergistic regional emission reductions in China: Network evolution, spatial and temporal characteristics, and driving factor

Ecological Indicators
Synergistic regional emission reduction (SRER) is an important part of the strategy to achieve carbon neutrality. In this paper, a system efficiency value-added model is proposed to measure the strength of SRER network relationships for 40,186 sets of ...
Bin Liao, Caihong Tian, Tian Zhou, Lei Han   +3 more
doaj   +1 more source

Scaling, Leakage Current Suppression, and Simulation of Carbon Nanotube Field-Effect Transistors

Nanomaterials
Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression ...
Weixu Gong, Zhengyang Cai, Shengcheng Geng, Zhi Gan, Junqiao Li, Tian Qiang, Yanfeng Jiang, Mengye Cai   +7 more
doaj   +1 more source

High field induced stress suppression of GIDL effects in TFTs

, 2010
Gate-Induced drain leakage (GIDL) is an unwanted short-channel effect that occurs at higher drain biases in an overdriven off state of a transistor. The GIDL is the result of a deep depletion region that forms in the drain at high drain-to-gate biases ...
McCabe, Andrew
core  

The Effect of Gate-Induced Drain Leakage (GIDL) on Scaled MOSFETS of Low Power Consumptions

, 2017
This project is aimed to study the impact of GateInduced Drain Leakage (GIDL) on scaled Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) for low power efficient application. The MOSFET is operated with low power consumption. Microchip industries
Hassan, Nornikman; Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Ngelayang, Thailis Bounya; Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Noor Azizi, Muhammad Syafiq; Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Putra, Mohd Hasbullah; Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Bolqiah Edrisa, Muhammad Zuhair; Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia.   +4 more
core  

Junction depth dependence of the gate induced drain leakage in shallow junction source/drain-extension nano-CMOS

, 2019
This study describes the dependence of the surface electric field to the junction depth of source/drain-extension, and the suppression of gate induced drain leakage (GIDL) in fully depleted shallow junction gate-overlapped source/drain-extension (SIDE ...
Song, SH, Jeong, YH, Kim, JC, Jung, SW
core   +1 more source

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

IEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

Characteristics of degradation under GIDL stress in ultrathin gate oxide LDD nMOSFET’s

Acta Physica Sinica, 2007
The threshold voltage (VTH) degradation have been investigated under GIDL　(gate induced drain leakage) stresse in LDD nMOSFET with 1.4　nm-thick gate oxide. The trapped holes and interface states generated in the stress process at interface around LDD overlapping region result in the increase in VTH.
null Chen Hai-Feng, null Hao Yue, null Ma Xiao-Hua, null Tang Yu, null Meng Zhi-Qin, null Cao Yan-Rong, null Zhou Peng-Ju   +6 more
openaire   +1 more source

High Field Induced Stress Suppression of GIDL Effects in Accumulation-Mode P-Channel TFTs

, 2010
By utilizing the effects of high energy, or "hot", electrons the GIDL current in an accumulation mode thin-film PFET can be suppressed. Both SOI and single crystal silicon-on-glass (SiOG) substrates were used to examine this effect. This suppression is
Karl Hirschman, Andrew McCabe, Robert G. Manley, Carlo Kosik Williams, J. Gregory Couillard   +4 more
core   +1 more source

Oxide-trap-induced instability in GIDL of thermally nitrided-oxide N-MOSFET's under stress

, 1992
Some holes created from band-to-band (B-B) tunneling in the deep-depletion region of the drain can be injected into the gate oxide and reduce the vertical field there. As a result, gate-induced drain leakage (GIDL) current decreases.
Lai, Pui T, Ma, ZJ, Cheng, YC
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