Results 61 to 70 of about 16,309 (85)

New observation and improvement in GIDL current of N-MOSFET's with various kinds of gate oxides under hot-carrier stress

, 1997
Degradation in gate-induced drain leakage (GIDL) current of n-MOSFET's with conventional SiO2 and oxynitride as gate dielectrics under hot-carrier stresses at different gate voltages is investigated.
Lai, PT, Zeng, X, Cheng, YC, Jingping, Xu   +3 more
core  

Novel cell-level erase for 3D NAND Flash memory

With advances in AI and the widespread adoption of NAND Flash technology imposing increasingly stringent performance requirements, conventional erase was unable to provide precise erasing in NAND Flash storage systems.
Guokun Ma, Wu Shiwen, Lin Lv, SiYuan Li, nanchang liang, Hao Wang, zhicheng liu, xiaoshan liu   +7 more
core   +1 more source

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory. [PDF]

Micromachines (Basel)
You K, Jin L, Jia J, Huo Z.
europepmc   +1 more source

Triple-Level Content-Addressable Vertical NAND Flash Memory. [PDF]

Adv Sci (Weinh)
Park SH, Im J, Yang Y, Koo RH, Ko J, Oh M, Shin D, Jung G, Lee JH.   +8 more
europepmc   +1 more source

Repurposing Si CMOS nonidealities for stochastic and analog image processing. [PDF]

Sci Adv
Kwak B, Koo RH, Han C, Shin Y, Choi J, Kim D, Lee J, Im J, Cho Y, Lee JH, Shin W, Kwon D.   +11 more
europepmc   +1 more source

Point mémoire analogique basse tension basé sur l'effet GIDL

, 2004
La mémoire est un élément incontournable de tout circuit électronique; le développement des applications analogiques basse puissance et basse tension sera conditionné par la disponibilité de points mémoire présentant ces mêmes caractéristiques.
Butaye, Olivier, Donckers, Nicolas, Flandre, Denis, TAISA 2004 - 5ème Colloque sur le Traitement Analogique de l'Information, du Signal et ses Applications, Verleysen, Michel   +4 more
core  

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology. [PDF]

Nanomaterials (Basel)
Radamson HH, Miao Y, Zhou Z, Wu Z, Kong Z, Gao J, Yang H, Ren Y, Zhang Y, Shi J, Xiang J, Cui H, Lu B, Li J, Liu J, Lin H, Xu H, Li M, Cao J, He C, Duan X, Zhao X, Su J, Du Y, Yu J, Wu Y, Jiang M, Liang D, Li B, Dong Y, Wang G.   +30 more
europepmc   +1 more source

High Mobility and GIDL Erase-Compatible Characteristics in Hybrid Channel (Poly-Si/IGO) for Ultrahigh 3D NAND Flash Memory Applications

ACS Applied Electronic Materials
In this paper, we propose a hybrid channel (HC) structure in which the poly-Si and indium gallium oxide (IGO) channels coexist to achieve high mobility and gate-induced-drain-leakage (GIDL) erase-compatible characteristics for 3D NAND flash memory ...
Yun Heub Song, Su-Hwan Choi, Sim Jaemin   +2 more
exaly   +3 more sources

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3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

2017 IEEE International Memory Workshop (IMW), 2017
The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation.
Christian Caillat, Kevin Beaman, Andrew Bicksler, Elisa Camozzi, Tecla Ghilardi, Guangyu Huang, Haitao Liu, Yifen Liu, Duo Mao, Salil Mujumdar, Niccolo Righetti, Matt Ulrich, Chandru Venkatasubramanian, Xiangyu Yang, Akira Goda, Srivardhan Gowda, Henok Mebrahtu, Hiroyuki Sanda, Yu Yuwen, Randy Koval   +19 more
exaly   +2 more sources