Results 61 to 70 of about 2,599 (207)

Characterization and Modeling of SH in Multi-Finger RF LDMOS Transistors Using BSIM-BULK Model

IEEE Journal of the Electron Devices Society
In this work, we present self-heating (SH) characterization and modeling of 130 nm Bipolar-CMOS-DMOS (BCD) technology node multi-finger Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) transistors using extensive DC and S-parameter ...
Ayushi Sharma, Shivendra Singh Parihar, Anirban Kar, Weike Wang, Kimihiko Imura, Yogesh Singh Chauhan   +5 more
doaj   +1 more source

Numerical investigation on L-shaped vertical field plate in high-voltage LDMOS

Results in Physics, 2019
In this work, an L-shaped vertical field plate (LVFP) is introduced in high-voltage lateral double-diffused MOSFET (LDMOS). The LVFP is embedded in an oxide trench that penetrates into the drift region. Compared with the conventional vertical field plate
Yue Hu, Zhifeng Liu, Shichang Chen, Jing Wang, Wen-Sheng Zhao, Gaofeng Wang   +5 more
doaj   +1 more source

An Analytical Breakdown Model for the SOI LDMOS With Arbitrary Drift Doping Profile by Using Effective Substrate Voltage Method

IEEE Journal of the Electron Devices Society, 2020
To elaborate on the relationship between sophisticated 2-D doping profile of drift region and device's breakdown behavior, a unified analytical model for the SOI LDMOS is developed in this paper.
Kemeng Yang, Yufeng Guo, Jun Zhang, Jiafei Yao, Man Li, Ling Du, Xiaoming Huang   +6 more
doaj   +1 more source

A novel ESD design for 800v Ldmos with robustness

, 2010
[[abstract]]ABSTRACT In the power management applications, the lateral double-diffusion MOS (LDMOS) transistor with high breakdown voltage has long been integrated monolithically in IC process.
Sarangua Enkhbaatar
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2. Pinning information Table 2. Pinning Pin Description Simplified outline Graphic symbol

, 2013
250 W LDMOS power transistor for base station applications at frequencies ...
Power Ldmos Transistor, High Efficiency
core   +1 more source

A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS Device

IEEE Journal of the Electron Devices Society, 2018
An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism.
Bing Wang, Zhigang Wang, James B. Kuo
doaj   +1 more source

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

IEEE Journal of the Electron Devices Society, 2019
An improved trench lateral double-diffused MOSFET (T-LDMOS) is proposed. It has a quasi vertical super junction (QVSJ) drift region and adopts a resistive field plate (RFP) to help QVSJ satisfy charge-balance.
Junji Cheng, Shiying Wu, Weizhen Chen, Haimeng Huang, Bo Yi   +4 more
doaj   +1 more source

Parameter Extraction for the PSPHV LDMOS Transistor Model

IEEE Journal of the Electron Devices Society, 2020
This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating.
Kejun Xia, Colin C. McAndrew, Ronald Van Langevelde   +2 more
doaj   +1 more source

LDMOS-transistorin hyväksyntäprosessi [PDF]

, 2018
Kaksi suurta tehotransistorivalmistajaa yhdistivät komponenttien valmistus-, testaus- ja kokoon-panolinjoja. Tämän johdosta täytyi uuden tyypin LDMOS-transistori testata Nokian tukiasema-tuotteissa.
Moilanen, Pekka
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Unclamped Inductive Switching Stress Failure Mechanism of LDMOS

, 2013
[[abstract]]The failure mechanism of Unclamped Inductive Switching (UIS) stress on Laterally Diffused MOS (LDMOS) device has been investigated first time. Failure in LDMOS has been compared with the Vertical DMOS.
Kumar, Vijay;Srinat, Grama;Shreyas, Grama Srinath;Khau, Chinmoy;Khaund, Chinmoy;Agarw, Neelam;Agarwal, Neelam;Nidhi, Karuna;Nidhi, Karuna;楊紹明;Yang, Shao-Ming;許健;Sheu, Gene
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