Results 61 to 70 of about 3,588 (218)

A novel SOI LDMOS with substrate field plate and variable-k dielectric buried layer

Results in Physics, 2018
A novel silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) structure has been proposed. The new structure features a substrate field plate (SFP) and a variable-k dielectric buried layer (VKBL).
Qi Li, Yi Wen, Fabi Zhang, Haiou Li, Gongli Xiao, Yonghe Chen, Tao Fu   +6 more
doaj   +1 more source

An 1 GHz class E LDMOS power amplifier [PDF]

33rd European Microwave Conference Proceedings (IEEE Cat. No.03EX723C), 2003
A class E power amplifier working at 1 GHz and with an LDMOS transistor as switching element has been developed.The circuit is implemented with lumped and distributed elements.An output power of 6.2 W at 69 %drain efficiency with a gain of 11 dB was obtained at 1 GHz.Both simulations and measurements of the amplifier are presented within this paper ...
Adahl, Andreas, Zirath, Herbert
openaire   +2 more sources

A Review of 5G Power Amplifier Design at cm‐Wave and mm‐Wave Frequencies

Wireless Communications and Mobile Computing, Volume 2018, Issue 1, 2018., 2018
The 5G wireless revolution presents some dramatic challenges to the design of handsets and communication infrastructures, as 5G targets higher than 10 Gbps download speed using millimeter‐wave (mm‐Wave) spectrum with multiple‐input multiple‐output (MIMO) antennas, connecting densely deployed wireless devices for Internet‐of‐Everything (IoE), and very ...
D. Y. C. Lie, J. C. Mayeda, Y. Li, J. Lopez, Jesus Fontecha   +4 more
wiley   +1 more source

High figure-of-merit SOI power LDMOS for power integrated circuits

Engineering Science and Technology, an International Journal, 2015
The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with ...
Yashvir Singh, Rahul Singh Rawat
doaj   +1 more source

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

IEEE Journal of the Electron Devices Society, 2020
We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization.
Ali Saadat, Maarten L. Van De Put, Hal Edwards, William G. Vandenberghe   +3 more
doaj   +1 more source

Bringing MRI to low‐ and middle‐income countries: Directions, challenges and potential solutions

NMR in Biomedicine, Volume 37, Issue 7, July 2024.
While MRI technology has advanced, several socioeconomic and technological challenges remain as barriers to MRI access globally. In this paper, we have described a holistic framework that tackles numerous different aspects to provide a structure for future research and development.
Sanjana Murali, Hao Ding, Fope Adedeji, Cathy Qin, Johnes Obungoloch, Iris Asllani, Udunna Anazodo, Ntobeko A. B. Ntusi, Regina Mammen, Thoralf Niendorf, Sola Adeleke   +10 more
wiley   +1 more source

Analysis of Kirk effect of an innovated high side Side-Isolated N-LDMOS device

MATEC Web of Conferences, 2016
An ESOA of LDMOS device is very critical for power device performance. Kirk effect is the one of the major problem which leads to poor ESOA performance. The cause of the problem mainly due to the high beta value of parasitic NPN transistor in the p-body.
Lai Ciou Jhong, Sheu Gene, Chien Ting Yao, Wu Chieh Chih, Lee Tzu Chieh, Deivasigamani Ravi, Wu Ching Yuan, Chandrashekhar, Yang Shao Ming   +8 more
doaj   +1 more source

Automatic optimal design of field plate for silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm

IET Power Electronics, Volume 17, Issue 4, Page 487-493, 18 March 2024.
In this paper, an automatic optimal design method for field plate (FP) in silicon on insulator lateral double‐diffused metal oxide semiconductor using simulated annealing algorithm is proposed. For a given device structure, the framework can automatically design the FP geometry parameters within the definite range that maximizes the device breakdown ...
Jing Chen, Renji Xia, Jinwen You, Qing Yao, Yuxuan Dai, Jun Zhang, Jiafei Yao, Yufeng Guo   +7 more
wiley   +1 more source

Interaction Between Hot Carrier Aging and PBTI Degradation in nMOSFETs: Characterization, Modelling and Lifetime Prediction [PDF]

, 2017
Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design.
Adamu-Lema, F., Aitken, R., Asenov, A., Benbakhti, B., Chandra, V., Duan, M., Groeseneken, G., Hao, Y., Ji, Z., Kaczer, B., Vigar, D., Zhang, J. C., Zhang, J. F., Zhang, W., Zheng, X.F.   +14 more
core   +1 more source

Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers

Results in Physics, 2020
Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper.
Yuan Wang, Shengdong Hu, Chang Liu, Jian'an Wang, Han Yang, Shenglong Ran, Jie Jiang, Gang Guo   +7 more
doaj   +1 more source