Results 121 to 130 of about 1,177 (162)

Mitigating Read Failures in STT-MRAM

2020 IEEE 38th VLSI Test Symposium (VTS), 2020
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging non-volatile memory technology, as a leading candidate to replace conventional on-chip memories due to its various advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility.
Nair, S. M., Bishnoi, R., Tahoori, M. B.
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Status and prospect for MRAM technology

2010 IEEE Hot Chips 22 Symposium (HCS), 2010
This article consists of a collection of slides from the author's conference presentation on the Everspin family of MRAM technology. Some of the specific topics discussed include: the current status of MRAM products; key MRAM features; current MRAM product operations; recent advancements in MRAM technology, and targeted markets.
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A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012
STT-MRAM has emerged as a compelling candidate for universal memory, but demands an advanced sensing circuit to achieve the proper sensing margin. In addition, STT-MRAM requires low-current sensing to avoid read disturbance. We report a novel sensing circuit that utilizes a source degeneration scheme and a balanced reference scheme.
Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung   +3 more
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Exploiting STT-MRAM for approximate computing

2017 22nd IEEE European Test Symposium (ETS), 2017
Spin Transfer Torque Magnetic RAM (STT-MRAM) is an emerging non-volatile memory technology and a potential candidate to replace SRAM in processor caches. However, STT-MRAM suffers from a high write latency and high write energy consumption which have to be addressed for energy-efficient on-chip caches.
Sayed, Nour, Oboril, Fabian, Shirvanian, Azadeh, Bishnoi, Rajendra, Tahoori, Mehdi B.   +4 more
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Cryogenic In-MRAM Computing

2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2021
Yaoru Hou, We Ge, Yanan Guo 0004, Lirida A. B. Naviner, You Wang 0002, Bo Liu 0019, Jun Yang 0006, Hao Cai 0001   +7 more
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MRAM defect analysis and fault modeling

2004 International Conferce on Test, 2005
With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The magnetic random access memory (MRAM) is considered one of the potential candidates that replace current on-chip memories (RAM, EEPROM, and flash memory) in the future.
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu   +6 more
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Embedded MRAM for high-speed computing

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
As the fabrication technology node shrinks down to 90nm or below, high standby power becomes one of the major critical issues for CMOS high-speed computing circuits (e.g. logic and cache memory) due to the high leakage currents. A number of non-volatile storage technologies such as FeRAM, MRAM, PCRAM and RRAM and so on, are under investigation to bring
Weisheng Zhao 0001, Yue Zhang 0010, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli   +11 more
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Monitoring Aging Defects in STT-MRAMs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
Identifying manufacturing defects in magnetic tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer (STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result inparametric deviations of the device that deteriorate over time.
Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev   +2 more
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A Parametric DFT Scheme for STT-MRAMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019
Process control and yield of spin torque transfer-magnetoresistive random access memory (STT-MRAM) array are of crucial importance in fabrication. While yield depends on the CMOS process variability, quality of the deposited MTJ film, and other process nonidealities, test platform can enable a parametric optimization and verification process using the ...
Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev   +2 more
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Multilevel Cell MRAMs

2017
Over the past three decades, several memory technologies have made their place in the market with varying degrees of commercial success, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), static random-access memory (SRAM), dynamic RAM (DRAM), and NAND/NOR flash memories, with varying ...
Brajesh Kumar Kaushik, Shivam Verma, Anant Aravind Kulkarni, Sanjay Prajapati   +3 more
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