Results 141 to 150 of about 16,097 (194)

Scaling Trends in NAND Flash

2018 IEEE International Electron Devices Meeting (IEDM), 2018
As the 2D NAND Flash scaling plateaued due to physical and electrical scaling limitations, 3D NAND emerged as a strong successor to continue the scaling trend. 3D NAND has rapidly achieved maturity and is already in the 3rd and 4th generation of technology with the total number of layers reaching 96 active layers.
K. Parat, A. Goda
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Flash Watermark: An Anticounterfeiting Technique for NAND Flash Memories

IEEE Transactions on Electron Devices, 2020
This article demonstrates a novel technique for watermarking commercial off-the-shelf NAND flash memory chips. The technique uses repeated program-erase stressing to selectively control the physical properties of the flash cells and hence imprint watermark information into the flash media in an irreversible manner.
Sadman Sakib, Aleksandar Milenkovic, Biswajit Ray   +2 more
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Radiation effects on NAND Flash memories

2010
Electronic chips operating at sea level are constantly bombarded by a shower of high-energy neutrons, which originate from the interactions of cosmic rays with the outer layers of the atmosphere. The neutron flux changes with altitude, reaching a peak very close to the cruise altitude of airplanes, posing an even more serious threat to avionics.
BAGATIN, MARTA, CELLERE, GIORGIO, GERARDIN, SIMONE, PACCAGNELLA, ALESSANDRO   +3 more
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Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory

2007 IEEE Symposium on VLSI Technology, 2007
Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps.
Donghwa Kwak, Jaekwan Park, Keonsoo Kim, Yongsik Yim, Soojin Ahn, Yoonmoon Park, Jinho Kim, Woncheol Jeong, Jooyoung Kim, Mincheol Park, Byungkwan Yoo, Sangbin Song, Hyunsuk Kim, Jaehwang Sim, Sunghyun Kwon, Byungjoon Hwang, Hyung-kyu Park, Sunghoon Kim, Yunkyoung Lee, Hwagyung Shin, Namsoo Yim, Kwangseok Lee, Minjung Kim, Youngho Lee, Jangho Park, Sangyong Park, Jaesuk Jung, Kinam Kim   +27 more
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NAND Flash Memory Revolution

2016 IEEE 8th International Memory Workshop (IMW), 2016
NAND Flash memory became a standard semiconductor nonvolatile memory. Everyone in the world has widely used NAND Flash memory in many applications, such as digital camera, USB drive, portable music player, smartphone, and tablet-PC. The cloud data server started to use SSD (Solid State Drive) which was based on NAND Flash memory.
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3D NAND Flash Memories

2018
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni, Seiichi Aritome, Luca Crippa   +2 more
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Modeling nand Flash Memories for IC Design

IEEE Electron Device Letters, 2008
In this letter, we present a compact model of NAND flash memory strings for circuit simulation purposes. This model is modular and easy to be implemented, and its parameters can be extracted through a simple procedure. It allows accurate simulation of NAND flash memories with a limited computational effort, taking into account capacitive coupling ...
LARCHER, Luca, PADOVANI, ANDREA, PAVAN, Paolo, P. FANTINI, A. CALDERONI, A. MAURI, A. BENVENUTI   +6 more
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NAND Flash Technology

2012
This chapter describes the basic operating principle and presents the major reliability and scaling limitations of floating gate NAND non-volatile memory as used in SSD applications. It further discusses charge trapping memory cells as a potential replacement for floating gate cells in the NAND array and evaluates the potential of both memory cell ...
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3D Stacked NAND Flash Memories

2016
Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
This paper analyzes the system-level performance of Storage Class Memory (SCM) / NAND flash hybrid solid-state drive (SSD). Four types of NAND flash, 1) 3-dimentional (3D) charge-trap (CT) Triple-Level Cell (TLC) [1], 2) 3D floating-gate (FG) TLC [2], 3) 2-dimentional (2D) FG TLC, and 4) 2D FG Multi-Level Cell (MLC) NAND flash are compared for various ...
Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui, Ken Takeuchi   +3 more
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