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Radiation effects on NAND Flash memories
2010Electronic chips operating at sea level are constantly bombarded by a shower of high-energy neutrons, which originate from the interactions of cosmic rays with the outer layers of the atmosphere. The neutron flux changes with altitude, reaching a peak very close to the cruise altitude of airplanes, posing an even more serious threat to avionics.
BAGATIN, MARTA +3 more
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Flash Watermark: An Anticounterfeiting Technique for NAND Flash Memories
IEEE Transactions on Electron Devices, 2020This article demonstrates a novel technique for watermarking commercial off-the-shelf NAND flash memory chips. The technique uses repeated program-erase stressing to selectively control the physical properties of the flash cells and hence imprint watermark information into the flash media in an irreversible manner.
Sadman Sakib +2 more
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2018 IEEE International Electron Devices Meeting (IEDM), 2018
As the 2D NAND Flash scaling plateaued due to physical and electrical scaling limitations, 3D NAND emerged as a strong successor to continue the scaling trend. 3D NAND has rapidly achieved maturity and is already in the 3rd and 4th generation of technology with the total number of layers reaching 96 active layers.
K. Parat, A. Goda
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As the 2D NAND Flash scaling plateaued due to physical and electrical scaling limitations, 3D NAND emerged as a strong successor to continue the scaling trend. 3D NAND has rapidly achieved maturity and is already in the 3rd and 4th generation of technology with the total number of layers reaching 96 active layers.
K. Parat, A. Goda
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Evolution of NAND Flash Memory Interface
2007In this paper, we describe the basics of NAND flash memory and describe the evolution of its interface to facilitate easy integration, to provide high bandwidth, to offer disk-like interface, and/or to guarantee interoperability.
Sang Lyul Min +2 more
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A superblock-based flash translation layer for NAND flash memory
Proceedings of the 6th ACM & IEEE International conference on Embedded software - EMSOFT '06, 2006In NAND flash-based storage systems, an intermediate software layer called a flash translation layer (FTL)is usually employed to hide the erase-before-write characteristics of NAND flash memory. This paper proposes a novel superblockbased FTL scheme, which combines a set of adjacent logical blocks into a superblock.
Jeong-Uk Kang +3 more
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An efficient NAND flash file system for flash memory storage
IEEE Transactions on Computers, 2006In this paper, we present an efficient flash file system for flash memory storage. Flash memory, especially NAND flash memory, has become a major method for data storage. Currently, a block level translation interface is required between an existing file system and flash memory chips due to its physical characteristics.
Seung-Ho Lim, Kyu Ho Park 0002
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NAND Flash Application and Solution
IEEE Solid-State Circuits Magazine, 2013The NAND flash memory cell concept invented by Prof. Fujio Masuoka [1] inherently had advantages of the scalability, low cost, high yield, fast programming and low power operation compared with other non-volatile memories. In addition to the technological advantages, the advent of new mobile applications created a ?killer? application of the NAND flash
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2012
This chapter describes the basic operating principle and presents the major reliability and scaling limitations of floating gate NAND non-volatile memory as used in SSD applications. It further discusses charge trapping memory cells as a potential replacement for floating gate cells in the NAND array and evaluates the potential of both memory cell ...
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This chapter describes the basic operating principle and presents the major reliability and scaling limitations of floating gate NAND non-volatile memory as used in SSD applications. It further discusses charge trapping memory cells as a potential replacement for floating gate cells in the NAND array and evaluates the potential of both memory cell ...
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Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory
2007 IEEE Symposium on VLSI Technology, 2007Multi-level NAND flash memories with a 38 nm design rule have been successfully developed for the first time. A breakthrough patterning technology of Self Aligned Double Patterning (SADP) together with ArF lithography is applied to three critical lithographic steps.
Donghwa Kwak +27 more
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FTL algorithms for NAND-type flash memories
Design Automation for Embedded Systems, 2011Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated ...
Se Jin Kwon +3 more
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