Results 101 to 110 of about 878 (167)

Design of Low-Latency Layered Normalized Minimum Sum Low-Density Parity-Check Decoding Based on Entropy Feature for NAND Flash-Memory Channel. [PDF]

Entropy (Basel)
Li Y, Hu H.
europepmc   +1 more source

A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs). [PDF]

Micromachines (Basel), 2019
Subbiah A, Ogunfunmi T.
europepmc   +1 more source

ReHypar: a recursive hybrid chunk partitioning method using NAND-flash memory SSD. [PDF]

ScientificWorldJournal, 2014
No J, Park SS, Lim CS.
europepmc   +1 more source

Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack. [PDF]

Nano Lett
Fernandes L, Wodzro S, Venkatesan P, Ravikumar P, Lee MY, Shon M, Chakraborty D, Song T, Kang S, Soliman S, Tian M, Yeager J, Adler J, Chen J, Wang Z, Wolfe D, Yu S, Padovani A, Datta S, Ray B, Khan A.   +20 more
europepmc   +1 more source

TiO₂ nanolayer-assisted top-interface engineering for disturbance-free FeFETs: a blueprint for future van der Waals memory. [PDF]

Nano Converg
Kang H, Kwak J, Kim G, Lee S, Kim Y, Park S, Lim S, Seo K, Kim W, Ha D, Ahn J, Jeon S.   +11 more
europepmc   +1 more source

A high-performance onboard computing architecture for autonomous satellite mission planning. [PDF]

Sci Rep
Rao J, Zhao W, Ma M, Xue G, Zhang J, Li S, Zhu Y, An J.   +7 more
europepmc   +1 more source

Recent progress in HfO₂-based ferroelectric devices with oxide semiconductor channels: a comprehensive review. [PDF]

Nanoscale Adv
Kang HY, Shin YH, Kim DE, Kwon DW, Jeong JK.   +4 more
europepmc   +1 more source

MoS₂ Channel-Enhanced High-Density Charge Trap Flash Memory and Machine Learning-Assisted Sensing Methodologies for Memory-Centric Computing Systems. [PDF]

Adv Sci (Weinh)
Kim KH, Park JH, Lee KJ, Seo JW, Kim YK, Choi J, Seo MJ, Jang BC.   +7 more
europepmc   +1 more source

Advancing the Frontiers of HfO₂-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]

Adv Mater
Zhou Z, Li L, Feng Y, Wang X, Zheng Z, Jiao L, Zheng H, Shi Y, Ang KW, Gong X.   +9 more
europepmc   +1 more source

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A strategy to emulate NOR flash with NAND flash

ACM Transactions on Storage, 2010
This work is motivated by a strong market demand for the replacement of NOR flash memory with NAND flash memory to cut down the cost of many embedded-system designs, such as mobile phones. Different from LRU-related caching or buffering studies, we are interested in prediction-based prefetching based on given execution traces of application executions.
Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo   +2 more
exaly   +3 more sources