Results 21 to 30 of about 29,727 (252)
On the capacity of multilevel NAND flash memory channels [PDF]
2016 IEEE International Symposium on Information Theory (ISIT), 2016 In this paper, we initiate a first information-theoretic study on multilevel NAND flash memory channels with intercell interference. More specifically, for a multilevel NAND flash memory channel under mild assumptions, we first prove that such a channel is indecomposable and it features asymptotic equipartition property; we then further prove that ...
Han, G, Kavcic, A, Li, Y
core +8 more sources
Analysis of vertical AND flash memory for energy-efficient, scalable, fast CIM beyond vertical NAND flash memory [PDF]
Nano ConvergenceCompute-in-memory (CIM) has emerged as a promising solution to mitigate the data movement bottleneck in von Neumann architectures. While vertical NAND (V-NAND) flash memory has been explored for CIM, its structural constraints, including pass-bias ...
Jonghyun Ko +9 more
doaj +2 more sources
IEEE Journal of the Electron Devices Society, 2022 In flash memory technology, mechanical stress is considered as one of the major factors that can influence the device performance. Furthermore, mechanical stress can have a greater impact on the electrical performance in 3D NAND than in 2D NAND because ...
Eun-Kyeong Jang +4 more
doaj +2 more sources
Impact of Program–Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability [PDF]
MicromachinesThree-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost.
Xuesong Zheng +6 more
doaj +2 more sources
Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme. [PDF]
Front Neurosci, 2020 A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic ...
Lee ST, Lee JH.
europepmc +2 more sources
NAND Flash Memory Organization and Operations [PDF]
Journal of Information Technology & Software Engineering, 2015 NAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density. NAND flash memory is a non-volatile type of memory and has low power consumption. The erasing of NAND Flash memory is based on a block-wise base.
Novotný, Radovan +2 more
openaire +3 more sources
Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems [PDF]
Sensors, 2014 While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash
Min Huang, Zhaoqing Liu, Liyan Qiao
doaj +2 more sources
Forensics and Anti-Forensics of a NAND Flash Memory: From a Copy-Back Program Perspective
IEEE Access, 2021 This paper proposes a safe copy-back program operation in a NAND flash memory, which is targeting digital forensics for a variety of reasons. Due to the background management operation of the NAND flash memory, the original data is highly likely to ...
Na Young Ahn, Dong Hoon Lee
doaj +2 more sources
Bilayer LDPC Codes Combined with Perturbed Decoding for MLC NAND Flash Memory [PDF]
EntropyThis paper presents a coding scheme based on bilayer low-density parity-check (LDPC) codes for multi-level cell (MLC) NAND flash memory. The main feature of the proposed scheme is that it exploits the asymmetric properties of an MLC flash channel and ...
Lingjun Kong +3 more
doaj +2 more sources
NAND Flash Memory Characterization [PDF]
, 2019 The NAND technology has become a popular research area and implementation choice due to its non-volatile flash memory characteristics. There are many engineering challenges when it comes to NAND technology. Some of the limiting factors are reducing the transistor width and increasing read and write performance. The device physics for NAND floating gate
Heer, Tanvir Singh
openaire +2 more sources