Results 81 to 90 of about 5,324 (209)
Mitigating NBTI in the physical register file through stress prediction
, 2012 Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future transistor generations.
Chakraborty, Koushik +7 more
core +1 more source
NBTI degradation in LTPS TFTs under mechanical tensile strain
, 2011 —This letter investigates the negative-bias tempera-ture instability (NBTI) degradation of p-channel low-temperature polycrystalline–silicon thin-film transistors (LTPS TFTs) under mechanical tensile stress. Experimental results reveal that the interface
Wei-che Hsu +10 more
core +1 more source
Applications of DCIV method to NBTI characterization
Microelectronics Reliability, 2007 Abstract The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO 2 gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, Δ V ...
Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA ( host institution ) +3 more
openaire +3 more sources
Algorithms, 2016 The reliability of Very Large Scale Integration (VLSI) circuits has become increasingly susceptible to transient faults induced by environmental noise with the scaling of technology.
Zhiming Yang +3 more
doaj +1 more source
Modeling of PMOS NBTI effect considering temperature variation [PDF]
, 2007 Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose a fast and ac-curate PMOS NBTI model, in which the temperature varia-tion and the ratio of ...
Luo, Hong +11 more
core +1 more source
An Application-Specific NBTI Ageing Analysis Method
, 2015 There is growing concern about time-dependentperformance variations of CMOS devices due to ageing-induceddelay degradation. One of the main causes of ageing is NegativeBias Temperature Instability (NBTI).
Zwolinski, Mark +2 more
core +2 more sources
Minimization of NBTI performance degradation using internal node control [PDF]
, 2009 —Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for circuits with standby-mode equipped functional units because these units can be
R.P. Dick +5 more
core +1 more source
The Scientific World Journal, 2014 We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the
H. Hussin +4 more
doaj +1 more source
NBTI-Aware Power Gating Design
, 2012 [[abstract]]A header-based power gating structure inserts PMOS as sleep transistors between the power rail and the circuit. Since PMOS sleep transistors in the functional mode are turned-on continuously, Negative Bias Temperature Instability (NBTI ...
M.C. Lee;Y.G. Chen;D.K.Huang;S.C. Chang
core
IEEE AccessIn this study, the bias temperature instability (BTI) of peripheral complementary metal–oxide semiconductor devices in a cell-on-peri (COP) structure is investigated under cryogenic conditions. First, positive BTI (PBTI) in the nMOSFET is found to
Jung Rae Cho +12 more
doaj +1 more source