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Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method [PDF]

Informacije MIDEM, 2020
N. Mitrović +4 more
doaj +1 more source

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD ...
Swati Deshwal +4 more
doaj +1 more source

Rejuvenation of nbti-impacted processors using evolutionary generation of assembler programs

, 2016
The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes.
SONZA REORDA, Matteo +13 more
core +1 more source

Gate insulator process dependent NBTI in SiON p-MOSFETs

, 2008
The material dependence of NBTI in SiON p-MOSFETs is studied using the UF-OTF IDLIN method. It is shown that the N density at the Si/SiON interface plays a very crucial role in determining the magnitude as well as the time, temperature and field ...
V. D. Maheta +3 more
core +1 more source

NBTI-Aware Power Gating Design

, 2012
[[abstract]]A header-based power gating structure inserts PMOS as sleep transistors between the power rail and the circuit. Since PMOS sleep transistors in the functional mode are turned-on continuously, Negative Bias Temperature Instability (NBTI ...
M.C. Lee;Y.G. Chen;D.K.Huang;S.C. Chang
core

Future Circular Collider: The NbTi based Hadron Collider (FCC-NbTi)

, 2019
This report describes a novel research infrastructure, based on a 100 km circumference circular tunnel and a hadron collider, using NbTi superconducting magnet technology, with centre-of-mass collision energy of 37.5 TeV, providing a total integrated ...
Benedikt, Michael
core

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning

, 2009
Random process variation and variability intrinsic to PMOS Negative Bias Temperature Instability (NBTI-induced statistical variation) are two major reliability concerns as transistor dimensions scales with technology.
Oates, Anthony S. +5 more
core +1 more source

NBTI-Aware Transient Fault Rate Analysis Method for Logic Circuit Based on Probability Voltage Transfer Characteristics

Algorithms, 2016
The reliability of Very Large Scale Integration (VLSI) circuits has become increasingly susceptible to transient faults induced by environmental noise with the scaling of technology.
Zhiming Yang, Junbao Li, Yang Yu, Xiyuan Peng +3 more
doaj +1 more source

Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

The Scientific World Journal, 2014
We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the
H. Hussin +4 more
doaj +1 more source

Analysis of Bias Temperature Instability in Peripheral CMOS Devices for Low-Temperature Memory Applications

IEEE Access
In this study, the bias temperature instability (BTI) of peripheral complementary metal–oxide semiconductor devices in a cell-on-peri (COP) structure is investigated under cryogenic conditions. First, positive BTI (PBTI) in the nMOSFET is found to
Jung Rae Cho +12 more
doaj +1 more source

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negative bias temperature instability

negative bias temperature instability nbti