Ultrafast switching and high-endurance nonvolatile memory enabled by intrinsic switchable polarization in semiconducting Janus monolayers. [PDF]
Duong NT +17 more
europepmc +1 more source
Dipole-Driven Charge Trapping in Monolayer Janus MoSSe for Ultrathin Nonvolatile Memory Devices. [PDF]
Ko EB +9 more
europepmc +1 more source
Emerging Nonvolatile Memory Technologies in the Future of Microelectronics. [PDF]
Katehi L +5 more
europepmc +1 more source
Investigation of Resistive Switching in Cu/a-SiC/P<sup>+</sup>-Si Structure for Multilevel Nonvolatile Memory Applications. [PDF]
Shao H +5 more
europepmc +1 more source
Hydrazine Intercalation into 2D MoTe<sub>2</sub> Field Effect Transistor as Charge Trapping Sites for Nonvolatile Memory Applications. [PDF]
Yuan L +6 more
europepmc +1 more source
Nonvolatile Memory Device with Designed Geometric Nanocrystal and its Analytical Modeling
Nonvolatile memory (NVM) characteristics are presented using well-ordered geometric Cr nanocrystal (NC) through the assistance of the block copolymer template.
Shin, Dong Ok +5 more
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Flexible BaTiO<sub>3</sub> Ferroelectric Nonvolatile Memory for Neuromorphic Computation. [PDF]
Peng Y +7 more
europepmc +1 more source
Bi<sub>2</sub>O<sub>2</sub>Se-Based Monolithic Floating-Gate Nonvolatile Memory with Enhanced Charge Retention and Switching Performance. [PDF]
Cheng CC +12 more
europepmc +1 more source
Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators. [PDF]
Lele AS, Zhang B, Khwa WS, Chang MF.
europepmc +1 more source
An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process
This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme.
Li, YL, Chinese Acad Sci, State Key Lab Superlattices & Microstruct, Inst Semicond, Beijing 100864, Peoples R China. +3 more
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