Results 181 to 190 of about 1,753,751 (305)
A serially reprogrammable nonvolatile program memory for an airborne digital radar processor
Includes bibliographical references (pages 58-59)This paper details the design and fabrication of a prototype 32Kx24\ud bit serially reprogrammable nonvolatile program memory for a\ud high-speed airborne digital radar processor.
Siering, Erik Richard
core
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
Neuron Circuit Based on a Split-gate Transistor with Nonvolatile Memory for Homeostatic Functions of Biological Neurons. [PDF]
Kim H, Woo SY, Kim H.
europepmc +1 more source
Serial nonvolatile 1024 bit MNOS memory
The characteristics and operation of a nonvolatile MNOS sequential memory designed and built by Sandia National Laboratories for DOD are described. First, a general description and block diagram are presented, followed by the power, voltage, clock and ...
Dodson, W. H., Sokel, R. J.
core
Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh +3 more
wiley +1 more source
Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States. [PDF]
Jeon J, Cho K, Kim S.
europepmc +1 more source
Tight Evaluation of Real-Time Task Schedulability for Processor's DVS and Nonvolatile Memory Allocation. [PDF]
Nam SA, Cho K, Bahn H.
europepmc +1 more source
The systematic design of memristor‐based neural network is provided by analog conductance state parameters to accurately emulate the software‐based high‐resolution weight at discrete device level. The requirement of discrete analog conductance of memristor device is measured as ≈50 states with nonlinearity value of ≈0.142 within the deviation range of ...
Jingon Jang, Yoonseok Song, Sungjun Park
wiley +1 more source
A Universal Strategy for Stretchable Polymer Nonvolatile Memory via Tailoring Nanostructured Surfaces. [PDF]
Ban C +9 more
europepmc +1 more source
A volatile‐switching compact model of electrochemical metallization memory cells for neuromorphic architecture is developed and validated by reliable reproduction of device characterization measurements: I−V sweeps, SET kinetics, relaxation dynamics.
Rana Walied Ahmad +4 more
wiley +1 more source

