Results 11 to 20 of about 10,455 (213)
Mitigating bit flips or single event upsets in epilepsy neurostimulators [PDF]
Epilepsy and Behavior Case Reports, 2016 Objectives: The objective of this study was to review software errors known as single event upsets (SEUs) or bit flips due to cosmic rays in epilepsy neurostimulators. Materials and methods: A case report of a single event upset or bit flip is discussed;
Alice X. Dong +4 more
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SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction [PDF]
MicromachinesThis paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs)
Tianwen Li, Jianbing Tian, Jingli Qi
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Fushe yanjiu yu fushe gongyi xuebao, 2021 This study investigates the AD574, a 12-bit analog/digital converter (ADC) produced by American Analog Devices, Inc. (ADI) using bipolar/I2L technology. The test samples are subjected to a total ionizing dose (TID) of 400 Gy(Si) under 60Co γ irradiation.
XIANG Chuanfeng +10 more
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IEEE Access, 2022 This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel.
Antonio Calomarde +3 more
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Novel Radiation Hardened SOT-MRAM Read Circuit for Multi-Node Upset Tolerance
IEEE Open Journal of Nanotechnology, 2022 The rapid transistor scaling and threshold voltage reduction pose several challenges such as high leakage current and reliability issues. These challenges also make VLSI circuits more susceptible to soft-errors, particularly when subjected to harsh ...
Alok Kumar Shukla +5 more
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Active Radiation-Hardening Strategy in Bulk FinFETs
IEEE Access, 2020 In this article, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates an electrical field that ...
Antonio Calomarde +3 more
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A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology
IET Circuits, Devices and Systems, 2021 Conventional flip‐flops are more vulnerable to particle strikes in a radiation environment. To overcome this disadvantage, in the literature, many radiation‐hardened flip‐flops (FFs) based on techniques like triple modular redundancy, dual interlocked ...
Sabavat Satheesh Kumar +4 more
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Study of single event upsets (SEUS) a survey and analysis [PDF]
, 2021 Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates.
openaire +1 more source
Upper Stage Rocket Computer Technology Based on Multi-redundancy and Reconfigurable [PDF]
Jisuanji gongcheng, 2016 Aiming at features of the upper stage rocket computer,such as strong real-time property,high reliability and space radiation resistance,a new computer technology based on redundanly and reconfiguration is proposed.This paper describes the key ...
QU Xi,HUANG Huimin,ZHANG Ning,YU Guoqiang
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Determination of the Sensitive Volume and Critical Charge for Induction of SEU in Nanometer SRAMs [PDF]
فصلنامه علوم و فناوری فضایی, 2023 In this paper, the sensitive volume and critical charge of a 65-nm CMOS SRAM as two important quantities in Single Event Upset (SEU) calculations have been determined. SEU is the most common event in space investigations.
Gholamreza Raisali +2 more
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