Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset [PDF]
Planar devices and FinFET devices exhibit significant differences in single-event upset (SEU) response and charge collection. However, the charge collection process during SEU in FinFET devices has not been thoroughly investigated. This article addresses
Hongwei Zhang +6 more
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Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell [PDF]
In recent years, graphene has received so much attention because of its superlative properties and its potential to revolutionize electronics, especially in VLSI. This study analyzes the effect of single-event upset (SEU) in an SRAM cell, which employs a
Naheem Olakunle Adesina
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Soft-Error-Resilient Static Random Access Memory with Enhanced Write Ability for Radiation Environments [PDF]
As semiconductor technologies advance, SRAM cells deployed in space systems face heightened sensitivity to radiation-induced soft errors. In conventional 6T SRAM, when high-energy particles strike sensitive nodes, single-event upsets (SEUs) may occur ...
Se-Yeon Park, Eun Gyo Jeong, Sung-Hun Jo
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SEU Hardened D Flip-Flop Design with Low Area Overhead [PDF]
D flip-flop (DFF) is the basic unit of sequential logic in digital circuits. However, because of an internal cross-coupled inverter pair, it can easily appear as a single event upset (SEU) when hit by high-energy particles, resulting in the error in the ...
Chenyu Yin +3 more
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Enhancing the Reliability of AD936x-Based SDRs for Aerospace Applications via Active Register Scrubbing and Autonomous Fault Recovery [PDF]
Single Event Upsets (SEUs) in Commercial Off-The-Shelf (COTS) Software-Defined Radios (SDRs) are frequent in a erospace applications, especially in GEO (Geostationary Orbit) orbit during severe solar activity, and can lead to unexpected register ...
Jinyang Wang, Zhugang Wang, Li Zhou
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A Lightweight Method for Detecting and Correcting Errors in Low-Frequency Measurements for In-Orbit Demonstrators [PDF]
In the pursuit of enhancing the technological maturity of innovative magnetic sensing techniques, opportunities presented by in-orbit platforms (IOD/IOV experiments) provide a means to evaluate their in-flight capabilities.
María-Ángeles Cifredo-Chacón +2 more
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Low power and high-speed quadrate node upset tolerant latch design using CNTFET [PDF]
Scalability, leakage, short-channel effects, and reliability problems are some of the difficulties facing the semiconductor industry as it continues to experience a reduction in size.
Shaik Asiya, Satheesh Kumar S
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Update of Single Event Effects Radiation Hardness Assurance of Readout Integrated Circuit of Infrared Image Sensors at Cryogenic Temperature [PDF]
This paper review presents Single Event Effects (SEE) irradiation tests under heavy ions of the test-chip of D-Flip-Flop (DFF) cells and complete readout integrated circuits (ROIC) as a function of temperature, down to 50 K.
Laurent Artola +9 more
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SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction [PDF]
This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs)
Tianwen Li, Jianbing Tian, Jingli Qi
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Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]
The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Lofti-Kamran, P. +13 more
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