Results 61 to 70 of about 264 (165)

Enhancing SEU tolerance efficacy in advanced FinFET FPGA devices using system-level fine-grained spatial redundancy techniques

open access: yesNuclear Engineering and Technology
This paper investigates the Single Event Upset (SEU) sensitivity, system-level hardening effectiveness, and potential applications of high-performance 16 nm Field Programmable Gate Arrays (FPGAs) in radiation environments.
Chang Cai   +11 more
doaj   +1 more source

USING THE SOCHI STAND TO CONFIRM THE IMMATIBILITY OF THE INTEGRATED CIRCUIT

open access: yesБезопасность информационных технологий
The paper analyzes the possible to apply of the SOCHI stand for the purpose of controlling the immutability of the chip`s topology in order trust (in reliable and safe operation).
Dmitry V. Bobrovsky   +6 more
doaj   +1 more source

A Portable, Compact, and Fault-Tolerant Processor for Spaceflight Applications

open access: yesAerospace
This paper presents the Goddard RISC-V (GRV) a compact, portable, and highly customizable fault-tolerant 32-bit RISC-V processor, specifically designed for embedded space applications. The design integrates advanced fault-tolerance mechanisms to mitigate
David Guzman-Garcia   +7 more
doaj   +1 more source

Radiation-Hardened 16T SRAM Cell with Improved Read and Write Stability for Space Applications

open access: yesApplied Sciences
The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry.
Jong-Yeob Oh, Sung-Hun Jo
doaj   +1 more source

From vulnerability to robustness: Radiation-hard isolation for BPR-enabled stacked nanosheet CFETs

open access: yesNuclear Engineering and Technology
The integration of Buried Power Rail (BPR) and Complementary FET (CFET) technologies is a promising way to improve power efficiency and circuit density in advanced logic devices.
Dongwook Kim   +4 more
doaj   +1 more source

A Comprehensive Methodology for Soft Error Rate (SER) Reduction in Clock Distribution Network

open access: yesChips
Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability
Jorge Johanny Saenz-Noval   +2 more
doaj   +1 more source

RHLP-18T: A Radiation-Hardened 18T SRAM with Enhanced Read Stability and Low Power Consumption

open access: yesApplied Sciences
Electronic equipment in space is constantly exposed to high-energy particles, which can induce Single Event Upsets (SEUs) in memory components, threatening system reliability.
Han-Gyeol Kim, Sung-Hun Jo
doaj   +1 more source

Atmospheric neutron inducing single event effects on AI chips manufacturing with 8 nm FinFET

open access: yesNuclear Engineering and Technology
--With the rapid advancement of artificial intelligence (AI) chips in diverse applications, single event effects (SEE) caused by high energy particles in ambient environment have emerged as a critical concern.
Yonghong Li   +7 more
doaj   +1 more source

A multi-node-upset-resilient 14T SRAM with high read stability for space applications

open access: yesNuclear Engineering and Technology
This paper proposes a voltage-booster read-decoupled radiation-hardened 14T (BDRH14T) SRAM cell. In harsh environments such as space, radiation can flip the stored data in memory cells, resulting in soft errors, including single-event upset (SEU) and ...
Sung-Jun Lim, Sung-Hun Jo
doaj   +1 more source

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