Results 71 to 80 of about 8,001,430 (204)
Abstract The European Commission asked EFSA to provide support in the framework of Article 43 of Regulation (EC) No 396/2005 for the preparation of the EU position for 57th Session of the Codex Committee on Pesticide Residues (CCPR). In the current report, EFSA provided comments and recommendations on the proposed Codex maximum residue limits (CXLs ...
European Food Safety Authority (EFSA)
wiley +1 more source
Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory [PDF]
We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence.
LaBel, Kenneth +7 more
core
Investigation of Radiation Hardened TFET SRAM Cell for Mitigation of Single Event Upset
This study analyzes the soft error sensitivity of SRAM cell which employs double-gate tunnel field effect transistor (DG TFET). The mitigation technique for the data recovery after the heavy ion strike is discussed.
M. Pown, B. Lakshmi
doaj +1 more source
Simulating Single Event Upset Rate with BERT
The circuit level modeling of single event effects is an area of on-giong research.
P. K. Ko +4 more
core
This paper investigates the Single Event Upset (SEU) sensitivity, system-level hardening effectiveness, and potential applications of high-performance 16 nm Field Programmable Gate Arrays (FPGAs) in radiation environments.
Chang Cai +11 more
doaj +1 more source
USING THE SOCHI STAND TO CONFIRM THE IMMATIBILITY OF THE INTEGRATED CIRCUIT
The paper analyzes the possible to apply of the SOCHI stand for the purpose of controlling the immutability of the chip`s topology in order trust (in reliable and safe operation).
Dmitry V. Bobrovsky +6 more
doaj +1 more source
A Portable, Compact, and Fault-Tolerant Processor for Spaceflight Applications
This paper presents the Goddard RISC-V (GRV) a compact, portable, and highly customizable fault-tolerant 32-bit RISC-V processor, specifically designed for embedded space applications. The design integrates advanced fault-tolerance mechanisms to mitigate
David Guzman-Garcia +7 more
doaj +1 more source
Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors
This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency.
Irom, Frokh +3 more
core
Radiation-Hardened 16T SRAM Cell with Improved Read and Write Stability for Space Applications
The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry.
Jong-Yeob Oh, Sung-Hun Jo
doaj +1 more source
Simulating single event upset error rate in large digital circuits
Using this new module of Berkeley Reliability Tools (BERT), user can predict the error rate due to single event upset (SEU) in large circuits. The error rate model described here used a well established methodology, but for the first time a different ...
P. K. Ko +4 more
core

