Results 81 to 90 of about 989 (213)

A Portable, Compact, and Fault-Tolerant Processor for Spaceflight Applications

Aerospace
This paper presents the Goddard RISC-V (GRV) a compact, portable, and highly customizable fault-tolerant 32-bit RISC-V processor, specifically designed for embedded space applications. The design integrates advanced fault-tolerance mechanisms to mitigate
David Guzman-Garcia, Ryan J. Ridley, George Suarez, Salman I. Sheikh, Matthew C. Daehn, Jeffrey J. Dumonthier, Georgia A. de Nolfo, John G. Mitchell   +7 more
doaj   +1 more source

Impact of D-Flip-Flop Architectures and Designs on Single-Event Upset Induced by Heavy Ions

, 2018
International audienceThis paper highlights the impact of design on the single-event upset (SEU) sensitivity of D-flip-flops (DFFs) used in a readout circuit (ROIC) under heavy ions. New experimental data obtained at the University of Louvain for several
S. Ducret, Hubert, Guillaume, Ahmad Al Youssef, Mekki, Julien, J. Mekki, Artola, Laurent, Ducret, Samuel, Ricard, Nicolas, L. Artola, Al Youssef, Ahmad, N. Ricard, G. Hubert   +11 more
core   +1 more source

Radiation-Hardened 16T SRAM Cell with Improved Read and Write Stability for Space Applications

Applied Sciences
The critical charge of sensitive nodes decreases as transistors scale down with the advancement of CMOS technology, making SRAM cells more susceptible to soft errors in the space industry.
Jong-Yeob Oh, Sung-Hun Jo
doaj   +1 more source

From vulnerability to robustness: Radiation-hard isolation for BPR-enabled stacked nanosheet CFETs

Nuclear Engineering and Technology
The integration of Buried Power Rail (BPR) and Complementary FET (CFET) technologies is a promising way to improve power efficiency and circuit density in advanced logic devices.
Dongwook Kim, Hanggyo Jung, Jimyeong Lee, Seungkyu Kim, Jongwook Jeon   +4 more
doaj   +1 more source

Simulating single event upset error rate in large digital circuits

, 1994
Using this new module of Berkeley Reliability Tools (BERT), user can predict the error rate due to single event upset (SEU) in large circuits. The error rate model described here used a well established methodology, but for the first time a different ...
P. K. Ko, PAVAN, Paolo, C. Hu, E. Minami, R. Tu   +4 more
core  

A Comprehensive Methodology for Soft Error Rate (SER) Reduction in Clock Distribution Network

Chips
Single Event Transients (SETs) in clock-distribution networks are a major source of soft errors in synchronous systems. We present a practical framework that assesses SET risk early in the design cycle, before layout and parasitics, using a Vulnerability
Jorge Johanny Saenz-Noval, Umberto Gatti, Cristiano Calligaro   +2 more
doaj   +1 more source

Predicting On-Orbit Static Single Event Upset Rates in Xilinx Virtex FPGAs

, 2006
Sponsorship: Department of Energy, Los Alamos National Laboratory. This document describes the methodology used to predict single-event upset rates for Xilinx Virtex FPGAs based on the CREME96 orbit modeling tool.
Engel, Joshua, Morgan, Keith S., Wirthlin, Michael J., Graham, Paul S.   +3 more
core  

Characterization of System on a Chip (SoC) Single Event Upset (SEU) Responses Using SEU Data, Classical Reliability Models, and Space Environment Data

, 2017
We propose a method for the application of single event upset (SEU) data towards the analysis of complex systems using transformed reliability models (from the time domain to the particle fluence domain) and space environment ...
Campola, Michael, Berg, Melanie, Xapsos, Michael, Label, Kenneth   +3 more
core  

RHLP-18T: A Radiation-Hardened 18T SRAM with Enhanced Read Stability and Low Power Consumption

Applied Sciences
Electronic equipment in space is constantly exposed to high-energy particles, which can induce Single Event Upsets (SEUs) in memory components, threatening system reliability.
Han-Gyeol Kim, Sung-Hun Jo
doaj   +1 more source

Dynamic partial reconfiguration scheme for fault-tolerant FFT processor based on FPGA

The Journal of Engineering, 2019
The fast Fourier transform FFT processor is an important part of the space real-time signal processing system based on field programmable gate array (FPGA).
Xin Wei, Yi Z Xie, Yu Xie, He Chen
doaj   +1 more source