Results 121 to 130 of about 253 (176)

Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs)

2008 IEEE International Symposium on Circuits and Systems, 2008
SRAM yield is very important from an economics viewpoint, because of the extensive use of memory in modern processors and SOCs. Therefore, SRAM stability analysis tools have become essential. SRAM stability analysis based on static noise margin (SNM) often results in pessimistic designs because SNM cannot capture the transient behavior of the noise ...
Rajesh Garg, null Peng Li, Sunil P. Khatri   +2 more
openaire   +1 more source

Single Event Upset (SEU) of Semiconductor Devices - A Summary of JPL Test Data

IEEE Transactions on Nuclear Science, 1983
A summary of the data on single event upset (bit flips) for sixt-y device types, having data storage elements, that were tested by JPL through May, 1982, is presented. The data were taken from fifteen accelerator tests with both protons and heavier ions.
Donald K. Nichols, William E. Price, Carl J. Malone   +2 more
openaire   +1 more source

Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices

2014 IEEE Radiation Effects Data Workshop (REDW), 2014
Results of neutron induced single event upset (SEU) testing of two Synchronous Burst Static Random Access Memory (SRAM) devices, the Galvantech GVT71128G36 128K x 36 and the GSI GS816273CC 256K x 72, and the internal RAM (iRAM) in the Texas Instruments SM32C6713BGDPA20EP Digital Signal Processor (DSP) are described.
Michael J. Tostanoski, Terrence F. Deaton, Roy E. Strayer, Rudolf Goldflam, Travis Z. Fullem   +4 more
openaire   +1 more source

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014
This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage ...
Wei Wei, Fabrizio Lombardi, Kazuteru Namba   +2 more
openaire   +1 more source

Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

IEEE Transactions on Nuclear Science, 2004
We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
P.K. Samudrala, J. Ramos, S. Katkoori
openaire   +1 more source

Techniques of Microprocessor Testing and SEU (Single Event Upset)-Rate Prediction.

1986
Abstract : Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this report we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the
Michael T. Marra, Wojciech A. Kolasinski, Rokutaro Koga   +2 more
openaire   +1 more source

Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), 2017
A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in
Chunyan Hu, Suge Yue, Shijin Lu
openaire   +1 more source

Ion beam induced charge collection (IBICC) microscopy of ICs: relation to single event upsets (SEU)

Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 1993
Abstract Single event upset (SEU) imaging is a new diagnostic technique recently developed using Sandia's nuclear microprobe. This technique directly images, with micron resolution, those regions within an integrated circuit which are susceptible to ion-induced malfunctions. Such malfunctions are an increasing threat to space-based systems which make
K.M. Horn, B.L. Doyle, F.W. Sexton, J.S. Laird, A. Saint, M. Cholewa, G.J.F. Legge   +6 more
openaire   +1 more source

Recent Trends in Parts SEU (Single Event Upset) Susceptibility from Heavy Ions.

1988
Abstract : JPL and Aerospace have collected an extensive set of heavy ion single event upset (SEU) test data since their joint publication in December 1985. This report presented trends in SEU susceptibility for state-of-the-art parts. An ongoing single event upset (SEU) program at JPL and the Aerospace Corporation is continuing in order to assess ...
W. A. Kolasinski, R. Koga, W. E. Price, L. S. Smith, D. K. Nichols   +4 more
openaire   +1 more source

Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021
Polar codes are used in 5G system for the transmission of control channels due to its excellent error correction capability for short sequence, and CRC assistant successive cancellation list (CA-SCL) decoders are commonly used in practical system. When applied in critical environment, e.g. space platform, the memories in the hardware polar decoder will
Zhen Gao, Ruize Wang, Haoyu Du, Pedro Reviriego   +3 more
openaire   +1 more source