Results 111 to 120 of about 962 (213)

TECHNIQUES TO FACILITATE HITLESS RECOVERY FROM A FLASH SINGLE EVENT UPSET (SEU) ERROR THROUGH VIRTUALIZATION [PDF]

Many embedded systems use an embedded MultiMediaCard (eMMC) as the main storage device for such systems. When the eMMC for an embedded system is connected to the host Central Processing Unit (CPU) through an intermediate device, such as a Universal ...
P Le, Son, Yoo, Jay, I Walker, Daniel, Thornburg, Mike, Chu, Mark, Cherukatt, Vinod, Yeevani, Ramesh, Agarwal, Manish, F Haase, Jason   +8 more
core   +1 more source

Reliability Analysis of the LEON3 Memory Subsystem Under Single-Event Upsets: Cache, AHB Interface, and Memory Controller Vulnerability

Information
This paper presents a register-transfer-level (RTL) fault injection study of the LEON3 processor’s internal memory subsystem under single-event upsets (SEUs). The analysis targets four key components: the instruction cache (I-cache), data cache (D-cache),
Afef Kchaou, Sehmi Saad, Hatem Garrab
doaj   +1 more source

Error detection and correction of single event upset (SEU) tolerant latch [PDF]

Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits.
Yakovlev A, Julai N, Bystrov A
core  

Single event upset correction in Virtex-2 FPGAs by scrubbing and TMR [PDF]

, 2005
Without the protection of atmosphere, space systems are bombarded with radiation. Single Event Upset (SEU) is an effect of radiation and can change the state of a flip-flop.
Bhat, Swadha
core   +1 more source

First Evaluation of the Single Event Upset (SEU) Risk for Electronics in the CMS Experiment [PDF]

, 1998
SEU error rates in the CMS tracker environment have been approximated with Monte Carlo simulations. The estimated upset rates for a submicron technology are 8.3 10-7 upsets/( bit s) at 4.9cm and 1.1 10-8 upsets/( bit s) at 49cm from the beam line ...
Detcheverry, C, Faccio, F, Huhtinen, Mika   +2 more
core  

A Radiation-Hardened Triple Modular Redundancy Design Based on Spin-Transfer Torque Magnetic Tunnel Junction Devices

Applied Sciences
Integrated circuits suffer severe deterioration due to single-event upsets (SEUs) in irradiated environments. Spin-transfer torque magnetic random-access memory (STT-MRAM) appears to be a promising candidate for next-generation memory as it shows ...
Shubin Zhang, Peifang Dai, Ning Li, Yanbo Chen   +3 more
doaj   +1 more source

ePosters Virtual

European Journal of Neurology, Volume 33, Issue S1, June 2026.
wiley   +1 more source

Single-Event Upset Analysis and Protection in High Speed Circuits [PDF]

, 2005
The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at
Natale, G., Benso, Alfredo, Hosseinabady, Mohammad, Lotfi-Kamran, Pejman, Carlo, S., Prinetto, Paolo   +5 more
core  

Radiation-Hardened 20T SRAM with Read and Write Optimization for Space Applications

Applied Sciences
With continued CMOS scaling, transistor miniaturization has significantly raised SRAM integration density while lowering the critical charge (Qc), increasing cell vulnerability to spaceborne high-energy particles.
Kon-Woo Kim, Eun Gyo Jeong, Sung-Hun Jo
doaj   +1 more source

SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS [PDF]

, 2008
The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU).
Ambat, Shadab Gopinath
core   +1 more source