Results 91 to 100 of about 8,001,430 (204)

A multi-node-upset-resilient 14T SRAM with high read stability for space applications

Nuclear Engineering and Technology
This paper proposes a voltage-booster read-decoupled radiation-hardened 14T (BDRH14T) SRAM cell. In harsh environments such as space, radiation can flip the stored data in memory cells, resulting in soft errors, including single-event upset (SEU) and ...
Sung-Jun Lim, Sung-Hun Jo
doaj   +1 more source

Atmospheric neutron inducing single event effects on AI chips manufacturing with 8 nm FinFET

Nuclear Engineering and Technology
--With the rapid advancement of artificial intelligence (AI) chips in diverse applications, single event effects (SEE) caused by high energy particles in ambient environment have emerged as a critical concern.
Yonghong Li, Jianan Tong, Weitao Yang, Zhiliang Hu, Lihua Mo, Tianjiao Liang, Chaohui He, Jinghui Lan   +7 more
doaj   +1 more source

Single Event Mirroring and DRAM Sense Amplifier Designs for Improved Single-Event-Upset Performance

, 2007
This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random ...
Lloyd W. Massengill, Kush Gulati, Ghasi R. Agrawal   +2 more
core  

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect. [PDF]

Micromachines (Basel), 2023
Yin C, Gao T, Wei H, Chen Y, Liu H.
europepmc   +1 more source

Experimental Heavy-Ion SEU Cross-Sections Of Sram Memory Components

, 2014
International audienceIn this work the heavy ion induced Single Event Upset (SEU) cross-sections and resulting failure rates of SRAM memory components were ...
Tsiligiannis, Georgios, Dilillo, Luigi, Kettunen, Heikki, Rossi, Mario, Virtanen, Ari, Gupta, Viyas, Javanainen, Arto, Bosser, Alexandre Louis   +7 more
core   +1 more source

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset. [PDF]

Micromachines (Basel), 2023
Yang W, Song W, Guo Y, Li Y, He C, Wu L, Wang B, Liu H, Shi G.   +8 more
europepmc   +1 more source

우주용 Shift Register의 Single Event Upset 분석에 관한 연구

, 2013
학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2013.2, [ vi, 54 p. ]In this paper, an analytic method of radiation effect of the shift register composed of the latch for space applications is presented.
Kang, Geun-Hun, 강근훈
core   +1 more source

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications. [PDF]

Micromachines (Basel), 2023
Yao R, Lv H, Zhang Y, Chen X, Zhang Y, Liu X, Bai G.   +6 more
europepmc   +1 more source

An SEU-Tolerant Cache for a RISC-V Core

Computers
The open RISC-V Instruction Set Architecture (ISA) is a versatile architecture with a growing number of implementations, including the aerospace sector, where tolerance to Single-Event Upset (SEU) faults is critical.
Ariel David Santana Gil, Salvador Ibarra Delgado, Julio Villalba Moreno, Remberto Sandoval Arechiga, Viktor Iván Rodriguez Abdalá, Manuel Hernández Calviño   +5 more
doaj   +1 more source

Reliability Analysis of the LEON3 Memory Subsystem Under Single-Event Upsets: Cache, AHB Interface, and Memory Controller Vulnerability

Information
This paper presents a register-transfer-level (RTL) fault injection study of the LEON3 processor’s internal memory subsystem under single-event upsets (SEUs). The analysis targets four key components: the instruction cache (I-cache), data cache (D-cache),
Afef Kchaou, Sehmi Saad, Hatem Garrab
doaj   +1 more source