Results 131 to 140 of about 264 (165)
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Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage ...
Wei Wei 0034 +2 more
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Techniques of Microprocessor Testing and SEU (Single Event Upset)-Rate Prediction.
1986Abstract : Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this report we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the
Michael T. Marra +2 more
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2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018
This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao 0001 +4 more
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This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao 0001 +4 more
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System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)
2019In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor ...
Marwan Ammar +3 more
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A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories
IEEE Transactions on Computers, 2016This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a ...
Wei Wei 0034 +3 more
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Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)
2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), 2017A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in
Chunyan Hu, Suge Yue, Shijin Lu
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IEEE Transactions on Nuclear Science, 1984
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk +2 more
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Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk +2 more
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SEU (Single Event Upset) Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors,
1986Abstract : A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches.
J. Cusick +3 more
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Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices
2014 IEEE Radiation Effects Data Workshop (REDW), 2014Results of neutron induced single event upset (SEU) testing of two Synchronous Burst Static Random Access Memory (SRAM) devices, the Galvantech GVT71128G36 128K x 36 and the GSI GS816273CC 256K x 72, and the internal RAM (iRAM) in the Texas Instruments SM32C6713BGDPA20EP Digital Signal Processor (DSP) are described.
Michael J. Tostanoski +4 more
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Recent Trends in Parts SEU (Single Event Upset) Susceptibility from Heavy Ions.
1988Abstract : JPL and Aerospace have collected an extensive set of heavy ion single event upset (SEU) test data since their joint publication in December 1985. This report presented trends in SEU susceptibility for state-of-the-art parts. An ongoing single event upset (SEU) program at JPL and the Aerospace Corporation is continuing in order to assess ...
W. A. Kolasinski +4 more
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