Results 151 to 160 of about 10,587 (214)

Research on Precise Attitude Measurement Technology for Satellite Extension Booms Based on the Star Tracker. [PDF]

Sensors (Basel)
Sang P, Liu W, Cao Y, Xue H, Li B.
europepmc   +1 more source

Single Event Upset (SEU) of Semiconductor Devices - A Summary of JPL Test Data

IEEE Transactions on Nuclear Science, 1983
A summary of the data on single event upset (bit flips) for sixt-y device types, having data storage elements, that were tested by JPL through May, 1982, is presented. The data were taken from fifteen accelerator tests with both protons and heavier ions.
Donald K. Nichols, William E. Price, Carl J. Malone   +2 more
exaly   +3 more sources

Single-Event Upset (SEU) in a Dram with On-Chip Error Correction

IEEE Transactions on Nuclear Science, 1987
The results are given of the first SEU measurements ever reported on IC devices with on-chip error correction. This method of SEU abatement could revolutionize the design of SEU-immune electronic systems.
J. A. Zoutendyk, H. R. Schwartz, R. K. Watson, Z. Hasnain, L. R. Nevill   +4 more
exaly   +3 more sources

Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop

Microelectronics Reliability, 2016
Abstract A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy.
K Sanchez, P Perdu, Chee Lip Gan
exaly   +3 more sources

An Adaptive Single Event Upset (SEU)-Hardened Flip-Flop Design

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019
In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering ...
Zhongjie Guo
exaly   +3 more sources

Single event upset (SEU) sensitivity dependence of linear integrated circuits (ICs) on bias conditions

IEEE Transactions on Nuclear Science, 1997
The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.
K B Crawford, W R Crain, S C Moss
exaly   +3 more sources

Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips

IEEE Transactions on Nuclear Science, 1986
A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator.
P Thieberger
exaly   +3 more sources

An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020
SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also ...
Zheng-Sheng Han, Xinyu Liu, Igor A Kharitonov   +2 more
exaly   +3 more sources