Results 161 to 170 of about 10,587 (214)
2021 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE), 2021 Kirolosse M Girgis +2 more
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Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021 Polar codes are used in 5G system for the transmission of control channels due to its excellent error correction capability for short sequence, and CRC assistant successive cancellation list (CA-SCL) decoders are commonly used in practical system. When applied in critical environment, e.g. space platform, the memories in the hardware polar decoder will
Zhen Gao 0005 +3 more
openaire +2 more sources
Investigation of single-event upset (SEU) in an advanced bipolar process
IEEE Transactions on Nuclear Science, 1988 An extensive analytical and experimental study of SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes. >
J.A. Zoutendyk +2 more
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Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014 This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage ...
Wei Wei 0034 +2 more
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Error detection and correction of single event upset (SEU) tolerant latch
2012 IEEE 18th International On-Line Testing Symposium (IOLTS), 2012 Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors.
Norhuzaimin Julai +2 more
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IEEE Transactions on Nuclear Science, 1987 Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk +3 more
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Measurement: Journal of the International Measurement Confederation, 2014
Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
Lorenzo Ciani, Marcantonio Catelani
exaly +3 more sources
Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
Lorenzo Ciani, Marcantonio Catelani
exaly +3 more sources
IEEE Transactions on Nuclear Science, 1984
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk +2 more
exaly +2 more sources
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk +2 more
exaly +2 more sources
2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018 This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao 0001 +4 more
openaire +2 more sources
IEEE Transactions on Nuclear Science, 2004
We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
Srinivas Katkoori
exaly +2 more sources
We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
Srinivas Katkoori
exaly +2 more sources