Results 161 to 170 of about 962 (213)
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Single-Event Upset (SEU) in a Dram with On-Chip Error Correction
IEEE Transactions on Nuclear Science, 1987The results are given of the first SEU measurements ever reported on IC devices with on-chip error correction. This method of SEU abatement could revolutionize the design of SEU-immune electronic systems.
J. A. Zoutendyk +4 more
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Single Event Upset (SEU) of Semiconductor Devices - A Summary of JPL Test Data
IEEE Transactions on Nuclear Science, 1983A summary of the data on single event upset (bit flips) for sixt-y device types, having data storage elements, that were tested by JPL through May, 1982, is presented. The data were taken from fifteen accelerator tests with both protons and heavier ions.
Donald K. Nichols +2 more
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An Adaptive Single Event Upset (SEU)-Hardened Flip-Flop Design
2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering ...
Man Zhang, ZhongJie Guo, WanCheng Xu
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Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop
Microelectronics Reliability, 2016Abstract A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy.
Chung Tah Chua +4 more
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IEEE Transactions on Nuclear Science, 1997
The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.
R. Koga +7 more
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The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.
R. Koga +7 more
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Measurement, 2014
Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
CIANI, LORENZO, CATELANI, MARCANTONIO
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Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
CIANI, LORENZO, CATELANI, MARCANTONIO
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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020
SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also ...
Ze-Xin Su +7 more
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SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also ...
Ze-Xin Su +7 more
openaire +3 more sources
IEEE Transactions on Nuclear Science, 1984
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk +2 more
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Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk +2 more
openaire +3 more sources
Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips
IEEE Transactions on Nuclear Science, 1986A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator.
J. A. Zoutendyk +5 more
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IEEE Transactions on Nuclear Science, 2004
We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
P.K. Samudrala, J. Ramos, S. Katkoori
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We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
P.K. Samudrala, J. Ramos, S. Katkoori
openaire +3 more sources