Results 181 to 190 of about 962 (213)

Techniques of Microprocessor Testing and SEU (Single Event Upset)-Rate Prediction.

1986
Abstract : Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this report we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the
Michael T. Marra, Wojciech A. Kolasinski, Rokutaro Koga   +2 more
openaire   +1 more source

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018
This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao 0001, Lina Yan, Jinhua Zhu, Ruishi Han, Pedro Reviriego   +4 more
openaire   +1 more source

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

IEEE Transactions on Computers, 2016
This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a ...
Wei Wei 0034, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi   +3 more
openaire   +1 more source

System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)

2019
In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor ...
Marwan Ammar, Ghaith Bany Hamad, Otmane Ait Mohamed, Yvon Savaria   +3 more
openaire   +2 more sources

Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), 2017
A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in
Chunyan Hu, Suge Yue, Shijin Lu
openaire   +1 more source

SEU (Single Event Upset) Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors,

1986
Abstract : A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches.
J. Cusick, C. King, W. A. Kolasinski, R. Koga   +3 more
openaire   +1 more source

Ion beam induced charge collection (IBICC) microscopy of ICs: relation to single event upsets (SEU)

Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 1993
Abstract Single event upset (SEU) imaging is a new diagnostic technique recently developed using Sandia's nuclear microprobe. This technique directly images, with micron resolution, those regions within an integrated circuit which are susceptible to ion-induced malfunctions. Such malfunctions are an increasing threat to space-based systems which make
K.M. Horn, B.L. Doyle, F.W. Sexton, J.S. Laird, A. Saint, M. Cholewa, G.J.F. Legge   +6 more
openaire   +1 more source

Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices

2014 IEEE Radiation Effects Data Workshop (REDW), 2014
Results of neutron induced single event upset (SEU) testing of two Synchronous Burst Static Random Access Memory (SRAM) devices, the Galvantech GVT71128G36 128K x 36 and the GSI GS816273CC 256K x 72, and the internal RAM (iRAM) in the Texas Instruments SM32C6713BGDPA20EP Digital Signal Processor (DSP) are described.
Michael J. Tostanoski, Terrence F. Deaton, Roy E. Strayer, Rudolf Goldflam, Travis Z. Fullem   +4 more
openaire   +1 more source

Recent Trends in Parts SEU (Single Event Upset) Susceptibility from Heavy Ions.

1988
Abstract : JPL and Aerospace have collected an extensive set of heavy ion single event upset (SEU) test data since their joint publication in December 1985. This report presented trends in SEU susceptibility for state-of-the-art parts. An ongoing single event upset (SEU) program at JPL and the Aerospace Corporation is continuing in order to assess ...
W. A. Kolasinski, R. Koga, W. E. Price, L. S. Smith, D. K. Nichols   +4 more
openaire   +1 more source

Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM

IEEE Transactions on Nuclear Science, 1985
Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and 0 ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device.
J. A. Zoutendyk, L. S. Smith, G. A. Soli, P. Thieberger, H. E. Wegner   +4 more
openaire   +1 more source