Results 181 to 190 of about 10,587 (214)
Diagnostic and error correction system for avionics devices in presence of single event upset (SEU)
, 2013 In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CATELANI, MARCANTONIO, CIANI, LORENZO
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Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs)
2008 IEEE International Symposium on Circuits and Systems, 2008SRAM yield is very important from an economics viewpoint, because of the extensive use of memory in modern processors and SOCs. Therefore, SRAM stability analysis tools have become essential. SRAM stability analysis based on static noise margin (SNM) often results in pessimistic designs because SNM cannot capture the transient behavior of the noise ...
Rajesh Garg +2 more
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Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
7th International Symposium on Quality Electronic Design (ISQED'06), 2006This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for reconfigurable ...
Sajid Baloch +2 more
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The Single Event Upset (SEU) Response to 590 MeV Protons
IEEE Transactions on Nuclear Science, 1984A recent test of ten device types exposed to 590 MeV protons at SINR (Swiss Institute of Nuclear Research, Villigen) is presented to clarify the picture of SEU response to higher energy protons, such as those found in galactic cosmic rays, solar flares and trapped radiation belts.
D. K. Nichols +3 more
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Techniques of Microprocessor Testing and SEU (Single Event Upset)-Rate Prediction.
1986Abstract : Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this report we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the
Michael T. Marra +2 more
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Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)
2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), 2017A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in
Chunyan Hu, Suge Yue, Shijin Lu
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System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)
2019In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor ...
Marwan Ammar +3 more
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Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices
2014 IEEE Radiation Effects Data Workshop (REDW), 2014Results of neutron induced single event upset (SEU) testing of two Synchronous Burst Static Random Access Memory (SRAM) devices, the Galvantech GVT71128G36 128K x 36 and the GSI GS816273CC 256K x 72, and the internal RAM (iRAM) in the Texas Instruments SM32C6713BGDPA20EP Digital Signal Processor (DSP) are described.
Michael J. Tostanoski +4 more
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