Results 171 to 180 of about 962 (213)
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2021 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE), 2021
Kirolosse M. Girgis +2 more
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Kirolosse M. Girgis +2 more
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Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021Polar codes are used in 5G system for the transmission of control channels due to its excellent error correction capability for short sequence, and CRC assistant successive cancellation list (CA-SCL) decoders are commonly used in practical system. When applied in critical environment, e.g. space platform, the memories in the hardware polar decoder will
Zhen Gao 0005 +3 more
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Single-Event-Upset (SEU) Awareness in FPGA Routing
2007 44th ACM/IEEE Design Automation Conference, 2007The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with ...
Shahin Golshan, Elaheh Bozorgzadeh
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Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs)
2008 IEEE International Symposium on Circuits and Systems, 2008SRAM yield is very important from an economics viewpoint, because of the extensive use of memory in modern processors and SOCs. Therefore, SRAM stability analysis tools have become essential. SRAM stability analysis based on static noise margin (SNM) often results in pessimistic designs because SNM cannot capture the transient behavior of the noise ...
Rajesh Garg +2 more
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Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
7th International Symposium on Quality Electronic Design (ISQED'06), 2006This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for reconfigurable ...
Sajid Baloch +2 more
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Error detection and correction of single event upset (SEU) tolerant latch
2012 IEEE 18th International On-Line Testing Symposium (IOLTS), 2012Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors.
Norhuzaimin Julai +2 more
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Investigation of single-event upset (SEU) in an advanced bipolar process
IEEE Transactions on Nuclear Science, 1988An extensive analytical and experimental study of SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes. >
J.A. Zoutendyk +2 more
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The Single Event Upset (SEU) Response to 590 MeV Protons
IEEE Transactions on Nuclear Science, 1984A recent test of ten device types exposed to 590 MeV protons at SINR (Swiss Institute of Nuclear Research, Villigen) is presented to clarify the picture of SEU response to higher energy protons, such as those found in galactic cosmic rays, solar flares and trapped radiation belts.
D. K. Nichols +3 more
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Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage ...
Wei Wei 0034 +2 more
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