Results 191 to 200 of about 962 (213)
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IEEE Transactions on Nuclear Science, 1987
Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk +3 more
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Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk +3 more
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2009 NASA/ESA Conference on Adaptive Hardware and Systems, 2009
This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these ...
Xiaoxuan She, P.K. Samudrala
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This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these ...
Xiaoxuan She, P.K. Samudrala
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2017 IEEE Radiation Effects Data Workshop (REDW), 2017
Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird +6 more
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Results of neutron induced single event upset testing of devices with embedded error correction codes are described. Specifically, Cypress CY7C1061GE30-10BVXI and CY7C1061GE-10BVXI 16-Mbit Static Random Access Memories (SRAMs), and a memory system, consisting of a Tundra Tsi107 PowerPC Host Bridge interfacing with nine Micron MT48LC32M8A2TG-75ITD 256 ...
John M. Bird +6 more
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Single event upset (SEU): Diagnostic and error correction system for avioncs device
2009In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CIANI, LORENZO +2 more
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Diagnostic and error correction system for avionics devices in presence of single event upset (SEU)
2013In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CATELANI, MARCANTONIO, CIANI, LORENZO
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Efficient protection of polar decoders against Single Event Upsets (SEUs) on user memories
Microelectronics Reliability, 2023Dong Tian +5 more
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Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022Semiu A. Olowogemo +4 more
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2022 Iranian International Conference on Microelectronics (IICM), 2022
Masume Soleimaninia +2 more
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Masume Soleimaninia +2 more
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2021 IEEE Nuclear and Space Radiation Effects Conference (NSREC), 2021
Pierre Maillard +3 more
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Pierre Maillard +3 more
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Single-Event-Upset (SEU) Mitigation Techniques for Routing Resources of SRAM-FPGA
International Journal of Advancements in Computing Technology, 2012Cheng Gao -, Wei Guo -, Jiaoying Huang -
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