Results 11 to 20 of about 2,860,882 (305)
Soft Error-Aware Design Optimization of Low Power and Time-Constrained Embedded Systems [PDF]
In this paper, we present the first study that examines the impact of application task mapping on the reliability of multiprocessor system-on-chip (MPSoC) in the presence of single-event upsets (SEUs).
Rishad A Shafik +5 more
core +2 more sources
Minimum symbol error rate turbo multiuser beamforming aided QAM receiver [PDF]
This paper studies a novel iterative soft interference cancellation (SIC) aided beamforming receiver designed for high-throughput quadrature amplitude modulation systems communicating over additive white Gaussian noise channels.
Chen, Sheng, Tan, S, Hanzo, L
core +3 more sources
Novel Radiation Hardened SOT-MRAM Read Circuit for Multi-Node Upset Tolerance
The rapid transistor scaling and threshold voltage reduction pose several challenges such as high leakage current and reliability issues. These challenges also make VLSI circuits more susceptible to soft-errors, particularly when subjected to harsh ...
Alok Kumar Shukla +5 more
doaj +1 more source
Deep neural networks (DNNs) have been successfully deployed in widespread domains, including healthcare applications. DenseNet201 is a new DNN architecture used in healthcare systems (i.e., presence detection of the surgical tool).
Khalid Adam +2 more
doaj +1 more source
Soft errors have become a critical challenge as a result of technology scaling. Existing circuit-hardening techniques are commonly associated with prohibitive overhead of performance, area, and power.
Tun Li, Qinhan Yu, Hai Wan, Sikun Li
doaj +1 more source
Blind Joint Soft-Detection Assisted Slow Frequency-Hopping Multicarrier DS-CDMA [PDF]
A novel multiple-access scheme based on slow frequency-hopping multicarrier direct-sequence, code-division multiple access (SFH/MC DS-CDMA) is proposed and investigated, which can be rendered compatible with the existing second-generation narrow-band ...
Yang, L-L., Hanzo, L.
core +2 more sources
Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects
In this paper, we compare how radiation-induced soft errors affect the execution results of user-level applications on different processor cores that implement the same instruction set architecture (ISA).
Hyungmin Cho
doaj +1 more source
CASH: correlation-aware scheduling to mitigate soft error impact on heterogeneous multicores
With the exponential increase in the number of transistors under fast-paced technology progress, the soft error induced reliability issue is becoming even more challenging in heterogeneous multicore processor design.
Jiajia Jiao +6 more
doaj +1 more source
Fast and Accurate Error Simulation for CNNs Against Soft Errors
The great quest for adopting AI-based computation for safety-/mission-critical applications motivates the interest towards methods for assessing the robustness of the application w.r.t. not only its training/tuning but also errors due to faults, in particular soft errors, affecting the underlying hardware. Two strategies exist: architecture-level fault
Bolchini C. +3 more
openaire +5 more sources
Control of the discretization error in computational biomechanics: a goal oriented approach for hyperelastic soft ...
Arnaud Lejeune (12251653) +4 more
core +1 more source

