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The concern for soft errors is not overblown
IEEE International Conference on Test, 2005., 2006Single event upsets in logic paths are an emerging concern for computing systems built in advanced CMOS technologies. Upset rates for latches used in sequential circuits are increasing, and combinatorial circuit elements will also become a factor for future technology nodes.
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SIMD-based soft error detection
Proceedings of the ACM International Conference on Computing Frontiers, 2016Soft error rates in processors have been increasing with decreasing feature size and larger chips. Software-only solutions have been proposed to deal with this problem, for instance via instruction duplication. However, this leads to significant overheads in performance and energy.
Zhi Chen 0001 +2 more
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Is the concern for soft-error overblown?
IEEE International Conference on Test, 2005., 2005This article gives a general perspective regarding soft error and how to deal with it. Finally it the author gives his position on issues in solving soft error problems.
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Managing Soft-Errors in Transactional Systems
2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014Multicore architectures are becoming increasingly prone to soft-errors – i.e., transient faults caused by external physical phenomena such as electric noise and cosmic particle strikes. With increasing core counts, the soft-error rate is growing due to the accelerating transistor density on chips.
Mohamed Mohamedin +2 more
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Effects of Soft Error to System Reliability
2011 IEEE Workshops of International Conference on Advanced Information Networking and Applications, 2011Soft errors on hardware could affect the reliability of computer system. To estimate system reliability, it is important to know the effects of soft errors to system reliability. This paper explores the effects of soft errors to computer system reliability. We propose a new approach to measure system reliability for soft error factor.
Lei Xiong, Qingping Tan, Jianjun Xu
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2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
This paper presents a construction of a flip-flop (FF) that works as a soft error tolerant FF in system operations and as a BILBO (Built-In Logic Block Observer) FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft error tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF.
Kazuteru Namba, Hideo Ito
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This paper presents a construction of a flip-flop (FF) that works as a soft error tolerant FF in system operations and as a BILBO (Built-In Logic Block Observer) FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft error tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF.
Kazuteru Namba, Hideo Ito
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Soft Error Hardening for Asynchronous Circuits
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty.
Weidong Kuang +2 more
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Soft Error Mitigation in Soft-Core Processors
2016This chapter aims to present different approaches and techniques available in literature regarding the fault mitigation on soft-core processors, with an especial emphasis on those ones involving hardware/software hybrid-based solutions.
Antonio Martínez-Álvarez +2 more
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Modeling Soft-Error Propagation in Programs
2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2018As technology scales to lower feature sizes, devices become more susceptible to soft errors. Soft errors can lead to silent data corruptions (SDCs), seriously compromising the reliability of a system. Traditional hardware-only techniques to avoid SDCs are energy hungry, and hence not suitable for commodity systems.
Guanpeng Li +4 more
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Combinational Logic Soft Error Correction
2006 IEEE International Test Conference, 2006We present two techniques for correcting radiation-induced soft errors in combinational logic ? Error Correction using Duplication, and Error Correction using Time-Shifted Outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude.
Subhasish Mitra +5 more
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