Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture. [PDF]
Zhang J +8 more
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Subnanosecond flash memory enabled by 2D-enhanced hot-carrier injection. [PDF]
Xiang Y +7 more
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A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays. [PDF]
Wang W, Li X, Chen L, Sun H, Zhang F.
europepmc +1 more source
68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI. [PDF]
Guo L +15 more
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Neuromorphic computing paradigms enhance robustness through spiking neural networks. [PDF]
Ding J, Yu Z, Liu JK, Huang T.
europepmc +1 more source
Dynamic Performance and Power Optimization with Heterogeneous Processing-in-Memory for AI Applications on Edge Devices. [PDF]
Jeon S, Lee K, Lee K, Lee W.
europepmc +1 more source
Low-Power Branch CNN Hardware Accelerator with Early Exit for UAV Disaster Detection Using 16 nm CMOS Technology. [PDF]
Liang YP, Chao WC, Chung CC.
europepmc +1 more source
Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors. [PDF]
Li X +6 more
europepmc +1 more source
A Survey of Emerging Memory in a Microcontroller Unit. [PDF]
Qi L, Fan J, Cai H, Fang Z.
europepmc +1 more source
Decentralized Distributed Sequential Neural Networks Inference on Low-Power Microcontrollers in Wireless Sensor Networks: A Predictive Maintenance Case Study. [PDF]
Bolat Y, Murray I, Ren Y, Ferdosian N.
europepmc +1 more source

