Results 141 to 150 of about 2,552 (174)
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Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the ...
Aditya Bansal +11 more
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Proceedings of the IEEE, 1999
This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced.
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This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced.
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2011 International Symposium on Electronic System Design, 2011
In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write
Mamatha Samson, Satyam Mandavalli
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In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write
Mamatha Samson, Satyam Mandavalli
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Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02, 2002
This paper presents a Dynamic V/sub t/ SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The V/sub t/ of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high V/sub t/ only when it is not likely to be accessed anymore ...
Chris H. Kim, Kaushik Roy
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This paper presents a Dynamic V/sub t/ SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The V/sub t/ of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high V/sub t/ only when it is not likely to be accessed anymore ...
Chris H. Kim, Kaushik Roy
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2010 23rd International Conference on VLSI Design, 2010
This paper describes the SRAM design concept in FinFETtechnologies using unique features of non-planar double-gated devices. The parameter space required to design FinFETs is explored.Variety of SRAM design techniques are presented exploiting the advantages of tied gate and independent gate controlled configurations.
Rajiv Joshi, Keunwoo Kim, Rouwaida Kanj
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This paper describes the SRAM design concept in FinFETtechnologies using unique features of non-planar double-gated devices. The parameter space required to design FinFETs is explored.Variety of SRAM design techniques are presented exploiting the advantages of tied gate and independent gate controlled configurations.
Rajiv Joshi, Keunwoo Kim, Rouwaida Kanj
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SRAM CP: A Charge Recycling Design Schema for SRAM
2006An adiabatic charge-pump based charge recycling design was proposed in [1]. It was shown to save upto 15% energy on several DSP systems with no performance loss. In this paper, we illustrate new charge source multiplexing techniques that are especially targeted towards SRAM arrays.
Ka-Ming Keung, Akhilesh Tyagi
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10th IEEE International NEWCAS Conference, 2012
A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.
Nayif Saleh +3 more
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A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.
Nayif Saleh +3 more
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2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
Current delivery is a major challenge in chip design. Reduction of the nominal voltage due to technology scaling has worsened the problem. Voltage stacking has been proposed as a way to alleviate the problem by delivering power in a serial rather than the conventional parallel way. Several studies have proposed techniques to stack logic designs.
Elnaz Ebrahimi +2 more
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Current delivery is a major challenge in chip design. Reduction of the nominal voltage due to technology scaling has worsened the problem. Voltage stacking has been proposed as a way to alleviate the problem by delivering power in a serial rather than the conventional parallel way. Several studies have proposed techniques to stack logic designs.
Elnaz Ebrahimi +2 more
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2016 8th International Symposium on Telecommunications (IST), 2016
Exploring possible vulnerabilities for making hardware Trojans helps designers to improve the security and trust of integrated circuits (ICs). This paper discusses the hardware Trojan possibility in SRAM to evaluate the security of SRAM and evaluates the effectiveness of existing detection methods.
Roghayeh Saeidi +1 more
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Exploring possible vulnerabilities for making hardware Trojans helps designers to improve the security and trust of integrated circuits (ICs). This paper discusses the hardware Trojan possibility in SRAM to evaluate the security of SRAM and evaluates the effectiveness of existing detection methods.
Roghayeh Saeidi +1 more
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2006 International Electron Devices Meeting, 2006
A nonvolatile SRAM cell with two back-up nonvolatile memory devices is proposed. This novel cell offers non-volatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty. A slight performance penalty is anticipated.
Wei Wang +7 more
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A nonvolatile SRAM cell with two back-up nonvolatile memory devices is proposed. This novel cell offers non-volatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty. A slight performance penalty is anticipated.
Wei Wang +7 more
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