Results 81 to 90 of about 30,204 (293)
Optoelectronic synaptic devices based on solution‐processed molecular telluride GST‐225 phase‐change inks are demonstrated for three‐factor learning. A global optical signal broadcast through a silicon waveguide induces non‐volatile conductance updates exclusively in locally electrically flagged memristors.
Kevin Portner +14 more
wiley +1 more source
Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu +17 more
wiley +1 more source
MarciaTesta: An Automatic Generator of Test Programs for Microprocessors' Data Caches [PDF]
SBST (Software Based Self-Testing) is an effective solution for in-system testing of SoCs without any additional hardware requirement. SBST is particularly suited for embedded blocks with limited accessibility, such as cache memories.
Stefano Di Carlo +9 more
core +1 more source
The possibility of using two physical unclonable functions (based on static random access memory and on the ring oscillators) to produce true random number sequences was investigated.
S. S. Zalivako, A. A. Ivaniuk
doaj
Spatially Modulated Morphotropic Phase Boundaries in a Compressively Strained Multiferroic Thin Film
ABSTRACT The coexisting rhombohedral‐like (R′, MA) and tetragonal‐like (T′, MC) monoclinic phases in compressively strained bismuth ferrite thin films exhibit exceptional piezoelectric and magnetic properties. While previous studies have largely focused on probing the morphotropic phase boundaries (MPBs) comprising ordered R′/T′ twins, their self ...
Ting‐Ran Liu +7 more
wiley +1 more source
16 x 1 nMOS Static Random Access Memory Design
A Static Random Access Memory (SRAM) was designed using a 2 micron minimum geometry, nMOS fabrication process on an Apollo design station. In addition to the SRAN integrated circuit, test structures were included to help characterize the process and ...
Dougherty, David W
core +1 more source
A fast half-subtractor using 8T static random access memory for in-memory computation [PDF]
The existing system for computation completely incorporates Von-Neumann architecture which has limitations with respect to its memory, parallelism and power constraints. This has affected the efficiency of the computing system.
Shylashree, Nagaraja +4 more
core +1 more source
Wafer‐scale two‐dimensioanl In2Se3 oxidized into InOx on sodium‐embedded beta‐alumina enables multifunctional reconfigurable electronics. Sodium ions accumulate within distinct spatial distribution under drain‐controlle and gate‐controlled operation. Drain‐control operation gives controllability of ultraviolet‐driven optoelectronic synaptic conductance
Jinhong Min +13 more
wiley +1 more source
With the rapid development of various technologies, processing large amounts of data has become essential. To address this trend, various high-density and high-performance memories have emerged.
Ho-Sung Lee +4 more
doaj +1 more source
This paper presents a digital microfluidics‐based technique for transferring and reconfiguring soft nanomembranes. Laser‐machined nanothin membranes are picked up, transported, and aligned via tailored surface tension and the actuation of water droplets, enabling the development of flexible electronics, the integration of functional materials on 3D ...
Quang Anh Nguyen +15 more
wiley +1 more source

