Results 41 to 50 of about 17,344,745 (166)
A binarized neural network (BNN) accelerator based on a processing-in-memory (PIM)/ computing-in-memory (CIM) architecture using ultralow-voltage retention static random access memory (ULVR-SRAM) is proposed for the energy minimum-point (EMP) operation ...
Yusaku Shiotsu, Satoshi Sugahara
doaj +1 more source
Advances in Bio‐Integrated Edge Computing Systems for Smart and Connected Health
This review explores advances in bio‐integrated edge computing for healthcare, focusing on co‐designing computing, sensing, and energy strategies to overcome integration and power challenges for optimized, decentralized operation. ABSTRACT Recent advances in bio‐integrated healthcare technologies have enabled continuous, high‐resolution monitoring and ...
Gyuwon Kim +4 more
wiley +1 more source
DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC [PDF]
Static Random Access Memory (SRAM) has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST) logic is proposed.
A. KISHORE KUMAR +3 more
doaj
Lightweight and Low-Latency AES Accelerator Using Shared SRAM
In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, the proposed AES accelerator is located within the slave wrapper of the static ...
Jae Seong Lee +2 more
doaj +1 more source
Robotics in Ionizing Radiation Environments: Vulnerabilities, Hardening, and Future Directions
Radiation exposure causes cumulative degradation in robotic sensors, actuators, and electronic logic, often leading to undetected failures. This study maps component vulnerabilities, evaluates hardening and shielding strategies, and identifies testing gaps that must be addressed to enable next‐generation radiation‐tolerant robotic systems.
Francis A. K. Djirackor +4 more
wiley +1 more source
Wafer‐Scale 3D Integration for High‐Density Multi‐Valued Neuromorphic Logic
Wafer‐scale 3D vertically integrated multi‐valued logic (MVL) circuits are realized by monolithically integrating a Te/IGZO heterojunction FET with an engineered Te pull‐up FET. Heterointerface‐mediated transport and optimized current matching enable stable ternary operation, while vertical stacking reduces circuit footprint and interconnect complexity,
Chang‐Hyeon Kim +5 more
wiley +1 more source
A Review on Enhancement of SRAM Memory Cell [PDF]
In this field research paper explores the design and analysis of Static Random Access Memory (SRAMs) that focuses on optimizing delay and power. CMOS SRAM cell consumes very little power and has less read and write time.
Kushwaha, Amrit Lal +1 more
core
: Memory circuits such as static random-access memory (SRAM) and dynamic random-access memory (DRAM) form an integral part of system design and contribute significantly to system-level power consumption. Memory operating speeds and power dissipation have
Rudresh T. K. +4 more
core +1 more source
A dual‐randomness hardware platform is demonstrated by integrating PUF and TRNG functionalities into mixed‐ZGO nanoclusters. By leveraging spatial and temporal stochasticity, the mixed‐ZGO NCs device enables both unique identification and random signal generation.
Seungme Kang +6 more
wiley +1 more source
Re‐Thinking Electronic Circuit Design Through Emerging Reconfigurable Field Effect Transistors
Graphical illustration of reconfigurable field effect transistor (RFET) operation modes, including n‐type, p‐type, and ambipolar transport, as well as their areas of application discussed in this review: digital circuit design, analog circuit design, post‐Shannon computing, and sensing. ABSTRACT Reconfigurable field‐effect transistors, short RFETs, are
Jens Trommer +19 more
wiley +1 more source

