Results 51 to 60 of about 17,344,745 (166)

Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation

IEEE Access, 2021
Near-threshold voltage ( $V_{th}$ ) operation is an effective method for lowering energy consumption. However, it increases the impact of $V_{th}$ variation significantly, which makes it difficult for previously proposed static random access memory ...
Ji Sang Oh, Juhyun Park, Keonhee Cho, Tae Woo Oh, Seong-Ook Jung   +4 more
doaj   +1 more source

An AI‐Driven Framework for Directed Self‐Assembly Toward Design‐Technology Co‐Optimization

Advanced Science, EarlyView.
An artificial intelligence (AI)‐driven closed‐loop framework integrates experiment, three‐dimensional physics‐based simulation, and template design for directed self‐assembly (DSA). Guided by experimental data, AI‐assisted calibration accelerates model optimization, supports morphology prediction, and identifies template windows.
Caiwei Shang, Yanting Xu, Yue Zhang, Yan Zhang, Jianfeng Li, Ming Li, Longlin Lei, Wenda Bao, Weixuan Zeng, Shisheng Xiong   +9 more
wiley   +1 more source

Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference

Advanced Electronic Materials, EarlyView.
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho, Dae‐won Kim, Yujin Kim, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi   +6 more
wiley   +1 more source

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

Stochastic‐MTJ Sampler Arrays for In‐Array Monte–Carlo Estimation

Advanced Electronic Materials, EarlyView.
A low‐energy‐barrier magnetic tunnel junction array is operated as a probability‐domain sampler: each cell's random switching, programmed through a shared digital‐to‐analog converter, makes the per‐column multiply–accumulate an unbiased Monte–Carlo expectation estimator that returns both a mean and a calibrated uncertainty.
Ran Zhang, Nellie Laleni, Sina Ranjbar, Andreas Tsiougkos, Nandakishor Yadav, Vasilis Pavlidis, Thomas Kämpfe   +6 more
wiley   +1 more source

A Scalable and Resource‐Efficient Pipelined p‐Computer for Probabilistic Ising Machines

Advanced Intelligent Systems, EarlyView.
(a) Block diagram of the portfolio optimization problem: given M assets, the goal is to determine the optimal weights w that maximize the expected return (based on the mean historical assets return u), while minimizing the risk, quantified by the assets covariance matrix S.
Deborah Volpe, Eleonora Raimondo, Andrea Grimaldi, Pedram Khalili Amiri, Stefano Chiappini, Anna Giordano, Mario Carpentieri, Hyunsoo Yang, Massimo Chiappini, Giovanni Finocchio   +9 more
wiley   +1 more source

Opportunities for 2D‐Material‐Based Multifunctional Devices and Systems in Bioinspired Neural Networks

Small, EarlyView.
Bio‐inspired computing offers a route to highly energy‐efficient artificial intelligence. The unique physical properties of two‐dimensional (2D) materials can further enhance such computing approaches. This perspective highlights recent developments in 2D materials‐based neuromorphic devices and discusses future opportunities for integrating such novel
Jin Feng Leong, Maheswari Sivan, Jieming Pan, Zihang Fang, Jianan Li, Zefeng Xu, Shi Zhao, Quanzhen Wan, Evgeny Zamburg, Aaron Voon‐Yew Thean   +9 more
wiley   +1 more source

16 x 1 nMOS Static Random Access Memory Design [PDF]

, 1988
A Static Random Access Memory (SRAM) was designed using a 2 micron minimum geometry, nMOS fabrication process on an Apollo design station. In addition to the SRAN integrated circuit, test structures were included to help characterize the process and ...
Dougherty, David W
core  

Attention‐Based Spatial–Temporal Model for the Entire Indoor Space Temperature Estimation

IEEJ Transactions on Electrical and Electronic Engineering, EarlyView.
This study proposes a novel attention‐based spatial–temporal model for indoor temperature estimation, which integrates positional encoding and an attention mechanism with a fully connected neural network. By jointly capturing temporal dynamics and spatial correlations, the model enables high‐resolution estimation of temperature fields across the entire
Goro Terumichi, Jiarui Li, Tatsuji Kimura, Hiroaki Nishi   +3 more
wiley   +1 more source

Rapid and Accurate Timing Modeling for SRAM Compiler

, 2012
[[abstract]]Static random access memory is usually used in the ASIC design. The performances of memory always play major role in the overall circuit. In this paper, we propose an efficient extrapolation-based timing modeling method for SRAM complier.
Yen-Yu Chen;Shi-Yu Huang;Yi-Chung Chang
core   +1 more source