Results 231 to 240 of about 24,777 (278)

Self-checking binary logic systems using ternary logic circuits

Canadian Electrical Engineering Journal, 1984
The present status of multivalued logic is highlighted in a Canadian context. A particular example is given of the use of ternary circuits in the solution of the problem of testability of binary logic, through the introduction of a new concept called 2-of-3-valued logic.
M. Hu, K. C. Smith
openaire   +1 more source

Logic synthesis of controllers for B-ternary asynchronous systems

Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), 2002
Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case.
Y. Nagata, D.M. Miller, M. Mukaidono
openaire   +1 more source

Experimental system of ternary logic optical computer with reconfigurability

SPIE Proceedings, 2009
An experimental system of a ternary logic optical computer, including its working principle, architecture and main components, is proposed. The main object of this paper is to give readers a holistic understanding of the ternary optical computer. This experimental system, which fully exploits the parallelism of optics, can have huge data bus width ...
Zhang-Yi Shen, Yi Jin, Jun-Jie Peng
openaire   +1 more source

Ternary simulation of digital systems in CAD programmable logic

Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2003
Here is considered the problems of interpretative and compilation simulation of digital systems. Investigated the influence of logic transformation of gate models. Offered procedures, which modify the method of ternary simulation and avoid incorrect execution of direct implication in the cubic coverage of the given gate structure. Here is some examples,
A.S. Shkil, V.V. Pobezenko, I.Y. Sysenko
openaire   +1 more source

A redundant binary adder using a symmetric ternary logic system

International Journal of Electronics, 1993
A construction method is described for a fast parallel adder by using a redundant binary code (RBC). The RBC used has a fixed radix 2 and a digit set {−1,0,1}. The fast parallel adder is composed of ternary-valued CMOS gate networks, which are used in the symmetric ternary logic system, and its construction can be optimized with them.
SHINSAKU HIGASHI, TAKEO MIYATA, KOUSUKE TSUKAMOTO, TAKEYUKI KOBAYASHI   +3 more
openaire   +1 more source

Comparative Analysis of Crosstalk Effects in Dielectric Inserted Horizontal andVertical Multi-layer GNR Interconnects for Ternary Logic System

ECS Journal of Solid State Science and Technology, 2022
In this work, the performance of copper (Cu), dielectric inserted horizontal graphene nanoribbon (Di-HGNR) interconnect and dielectric inserted vertical graphene nanoribbon (Di-VGNR) interconnects are investigated using active shielding and passive shielding techniques.
Gurijala Deepthi, Madhavi Tatineni
openaire   +1 more source

Simulation of Ternary CMOS Schemes for Many-Valued Logic Systems

2019 IEEE 31st International Conference on Microelectronics (MIEL), 2019
Of interest is the possibility of implementing many-valued logic systems using traditional CMOS technologies. We considered an example of the implementation of three-valued logic elements based on symmetric 3vL logic using the values {-,0,+}, {-1.0, + 1}, {1,0,1}, {1,0,1} etc.
A. A. Krasnyuk, A. G. Prozorova
openaire   +1 more source

Ternary Logic Signals Transmission Based on a Unified Chaotic System

2006 International Conference on Communications, Circuits and Systems, 2006
In this paper, we present a method for transmitting ternary logic digital signals based on chaos masking, using a new unified chaotic system. The unified chaotic system is in the form of a general Lorenz system, which can generate the dynamics of Lorenz system, Chen system or Lu system, controlled by a simple analog switch.
Wenbo Liu, Wallace S. Tang, Guanrong Chen   +2 more
openaire   +1 more source

On constructing intellectual systems in ternary logic

Programming and Computer Software, 2014
The paper shows that it is possible to develop an intelligent system on a production knowledge model using three-valued logic, which operates with the states "truth, false, possible". A method is proposed for constructing intelligent systems that are free from contradictions and are capable of not only extracting facts but also explaining what facts ...
openaire   +1 more source

Design of an asynchronous digital system with B-ternary logic

Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002
Some of the recent digital systems have a serious clock skew problem which comes from huge hardware implementations and high speed operations in VLSI's. To overcome this problem, clock distribution techniques and more notably, asynchronous system design methodologies, have been investigated.
Y. Nagata, M. Mukaidono
openaire   +1 more source